- 您現(xiàn)在的位置：買賣IC網 > PDF目錄368958 > 28F640J5 Dual-Slot, PCMCIA Analog Power Controller PDF資料下載
參數(shù)資料
| 型號： | 28F640J5 |
| 英文描述： | Dual-Slot, PCMCIA Analog Power Controller |
| 中文描述： | 28F640J5 -英特爾StrataFlash內存技術，32和64兆比特 |
| 文件頁數(shù)： | 40/53頁 |
| 文件大?。?/td> | 306K |
| 代理商： | 28F640J5 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁當前第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁
INTEL
StrataFlash MEMORY TECHNOLOGY, 32 AND 64 MBIT
E
5.0 DESIGN CONSIDERATIONS
40
PRELIMINARY
5.1
Three-Line Output Control
The device will often be used in large memory
arrays. Intel provides five control inputs (CE
0
, CE
1
,
CE
2
, OE#, and RP#) to accommodate multiple
memory connections. This control provides for:
a.
b.
Lowest possible memory power dissipation.
Complete
assurance
contention will not occur.
that
data
bus
To use these control inputs efficiently, an address
decoder should enable the device (see Table 2,
Chip Enable Truth Table) while OE# should be
connected to all memory devices and the system’s
READ# control line. This assures that only selected
memory devices have active outputs while de-
selected memory devices are in standby mode.
RP# should be connected to
POWERGOOD signal to prevent unintended writes
during system power transitions. POWERGOOD
should also toggle during system reset.
the system
5.2
STS and Block Erase, Program,
and Lock-Bit Configuration
Polling
STS is an open drain output that should be
connected to V
CCQ
by a pull-up resistor to provide a
hardware method of detecting block erase,
program, and lock-bit configuration completion. In
default mode, it transitions low after block erase,
program, or lock-bit configuration commands and
returns to High Z when the WSM has finished
executing the internal algorithm. For alternate
configurations of the STS pin, see the Configuration
command.
STS can be connected to an interrupt input of the
system CPU or controller. It is active at all times.
STS, in default mode, is also High Z when the
device is in block erase suspend (with programming
inactive) or in reset/power-down mode.
5.3
Power Supply Decoupling
Flash memory power switching characteristics
require
careful
device
designers are interested in three supply current
issues; standby current levels, active current levels
and transient peaks produced by falling and rising
edges of CE
0
, CE
1
, CE
2
, and OE#. Transient
current magnitudes depend on the device outputs’
capacitive and inductive loading. Two-line control
and proper decoupling capacitor selection will
suppress transient voltage peaks. Since Intel
StrataFlash memory devices draw their power from
three V
CC
pins (these devices do not include a V
PP
pin), it is recommended that systems without
separate power and ground planes attach a 0.1 μF
ceramic capacitor between each of the device’s
three V
CC
pins (this includes V
CCQ
) and ground.
These high-frequency, low-inductance capacitors
should be placed as close as possible to package
leads on each StrataFlash device. Each device
should have a 0.1 μF ceramic capacitor connected
between its V
CC
and GND. These high-frequency,
low inductance capacitors should be placed as
close as possible to package leads. Additionally, for
every eight devices, a 4.7 μF electrolytic capacitor
should be placed between V
CC
and GND at the
array’s power supply connection. The bulk capacitor
will overcome voltage slumps caused by PC board
trace inductance.
decoupling.
System
5.4
V
CC
, V
PEN
, RP# Transitions
Block erase, program, and lock-bit configuration are
not guaranteed if V
PEN
or V
CC
falls outside of the
specified operating ranges, or RP#
≠
V
IH
or V
HH
. If
RP# transitions to V
IL
during block erase, program,
or lock-bit configuration, STS (in default mode) will
remain low for a maximum time of t
PLPH
+ t
PHRH
until the reset operation is complete. Then, the
operation will abort and the device will enter
reset/power-down mode. The aborted operation
may
leave
data
partially
programming, or partially altered after an erase or
lock-bit configuration. Therefore, block erase and
lock-bit configuration commands must be repeated
after normal operation is restored. Device power-off
or RP# = V
IL
clears the status register.
corrupted
after
相關PDF資料 |
PDF描述 |
|---|---|
| 28LV010RT2DB20 | 3.3V 1 Megabit (128K x 8-Bit) EEPROM |
| 28LV010 | 3.3V 1 Megabit (128K x 8-Bit) EEPROM |
| 28LV010RPDB20 | 3.3V 1 Megabit (128K x 8-Bit) EEPROM |
| 28LV010RPDB25 | 3.3V 1 Megabit (128K x 8-Bit) EEPROM |
| 28LV010RPDE20 | 3.3V 1 Megabit (128K x 8-Bit) EEPROM |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| 28F640L18 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:StrataFlash Wireless Memory |
| 28F640L30 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:1.8 Volt Intel StrataFlash㈢ Wireless Memory with 3.0-Volt I/O (L30) |
| 28F640P3 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel StrataFlash Embedded Memory |
| 28F640W30 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:1.8 Volt Intel Wireless Flash Memory with 3 Volt I/O and SRAM (W30) |
| 28F650 | 制造商:Cinch Connectors 功能描述:1 Lug Terminal Strip |
發(fā)布緊急采購，3分鐘左右您將得到回復。