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參數(shù)資料
| 型號： | 28F640J5 |
| 英文描述： | Dual-Slot, PCMCIA Analog Power Controller |
| 中文描述： | 28F640J5 -英特爾StrataFlash內(nèi)存技術，32和64兆比特 |
| 文件頁數(shù)： | 12/53頁 |
| 文件大小： | 306K |
| 代理商： | 28F640J5 |
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INTEL
StrataFlash MEMORY TECHNOLOGY, 32 AND 64 MBIT
E
V
PENH
on V
PEN
enables successful block erasure,
programming,
and
lock-bit
configuration.
All
functions
associated
with
altering
memory
contents
—block
erase,
program,
lock-bit
configuration—are accessed via the CUI and
verified through the status register.
12
PRELIMINARY
Commands are written using standard micro-
processor write timings. The CUI contents serve as
input to the WSM, which controls the block erase,
program, and lock-bit configuration. The internal
algorithms are regulated by the WSM, including
pulse repetition, internal verification, and margining
of data. Addresses and data are internally latched
during program cycles.
Interface software that initiates and polls progress
of block erase, program, and lock-bit configuration
can be stored in any block. This code is copied to
and executed from system RAM during flash
memory updates. After successful completion,
reads are again possible via the Read Array
command. Block erase suspend allows system
software to suspend a block erase to read or
program data from/to any other block.
2.1
Data Protection
Depending on the application, the system designer
may choose to make the V
PEN
switchable (available
only when memory block erases, programs, or lock-
bit configurations are required) or hardwired to
V
PENH
. The device accommodates either design
practice and encourages optimization of the
processor-memory interface.
When V
PEN
≤
V
PENLK
, memory contents cannot be
altered. The CUI’s two-step block erase, byte/word
program, and lock-bit configuration command
sequences provide protection from unwanted
operations even when V
PENH
is applied to V
PEN
. All
program functions are disabled when V
CC
is below
the write lockout voltage V
LKO
or when RP# is V
IL
.
The device’s block locking capability provides
additional protection from inadvertent code or data
alteration by gating erase and program operations.
3.0 BUS OPERATION
The local CPU reads and writes flash memory
in-system. All bus cycles to or from the flash
memory conform to standard microprocessor bus
cycles.
64-Kword Block
64-Kword Block
64-Kword Block
64-Kword Block
31
1
0
63
Word Wide (x16) Mode
1FFFFF
1F0000
3FFFFF
3F0000
01FFFF
010000
000000
A [22-1]: 64-Mbit
A [21-1]: 32-Mbit
128-Kbyte Block
128-Kbyte Block
128-Kbyte Block
128-Kbyte Block
31
1
0
63
Byte-Wide (x8) Mode
3FFFFF
3E0000
7FFFFF
7E0000
03FFFF
020000
000000
A [22-0]: 64-Mbit
A [21-0]: 32-Mbit
3
6
0606_05
Figure 5. Memory Map
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| 28F640L18 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:StrataFlash Wireless Memory |
| 28F640L30 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:1.8 Volt Intel StrataFlash㈢ Wireless Memory with 3.0-Volt I/O (L30) |
| 28F640P3 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel StrataFlash Embedded Memory |
| 28F640W30 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:1.8 Volt Intel Wireless Flash Memory with 3 Volt I/O and SRAM (W30) |
| 28F650 | 制造商:Cinch Connectors 功能描述:1 Lug Terminal Strip |
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