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| 型號： | 28F640J5 |
| 英文描述： | Dual-Slot, PCMCIA Analog Power Controller |
| 中文描述： | 28F640J5 -英特爾StrataFlash內(nèi)存技術(shù)，32和64兆比特 |
| 文件頁數(shù)： | 13/53頁 |
| 文件大?。?/td> | 306K |
| 代理商： | 28F640J5 |
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E
INTEL
StrataFlash MEMORY TECHNOLOGY, 32 AND 64 MBIT
13
PRELIMINARY
Table 2. Chip Enable Truth Table
(1,2)
CE
2
CE
1
CE
0
DEVICE
V
IL
V
IL
V
IL
Enabled
V
IL
V
IL
V
IH
Disabled
V
IL
V
IH
V
IL
Disabled
V
IL
V
IH
V
IH
Disabled
V
IH
V
IL
V
IL
Enabled
V
IH
V
IL
V
IH
Enabled
V
IH
V
IH
V
IL
Enabled
V
IH
V
IH
V
IH
Disabled
NOTE:
1.
See Application Note
AP-647 Intel StrataFlash
Memory Design Guide
for typical CE configurations.
For single-chip applications CE
2
and CE
1
can be
strapped to GND.
2.
3.1
Read
Information can be read from any block, query,
identifier codes, or status register independent of
the V
PEN
voltage. RP# can be at either V
IH
or V
HH
.
Upon initial device power-up or after exit from
reset/power-down mode, the device automatically
resets to read array mode. Otherwise, write the
appropriate read mode command (Read Array,
Read Query, Read Identifier Codes, or Read Status
Register) to the CUI. Six control pins dictate the
data flow in and out of the component: CE
0
, CE
1
,
CE
2
, OE#, WE#, and RP#. The device must be
enabled (see Table 2, Chip Enable Truth Table),
and OE# must be driven active to obtain data at the
outputs. CE
0
, CE
1
, and CE
2
are the device
selection controls and, when enabled (see Table 2,
Chip Enable Truth Table), select the memory
device. OE# is the data output (DQ
0
–DQ
15
) control
and, when active, drives the selected memory data
onto the I/O bus. WE# must be at V
IH
.
3.2
Output Disable
With OE# at a logic-high level (V
IH
), the device
outputs are disabled. Output pins DQ
0
–DQ
15
are
placed in a high-impedance state.
3.3
Standby
CE
0
, CE
1
, and CE
2
can disable the device (see
Table 2,
Chip Enable Truth Table
) and place it in
standby mode which substantially reduces device
power consumption. DQ
0
–DQ
15
outputs are placed
in a high-impedance state independent of OE#. If
deselected during block erase, program, or lock-bit
configuration, the WSM continues functioning, and
consuming active power until the operation
completes.
3.4
Reset/Power-Down
RP# at V
IL
initiates the reset/power-down mode.
In read modes, RP#-low deselects the memory,
places output drivers in a high-impedance state,
and turns off numerous internal circuits. RP# must
be held low for a minimum of t
PLPH
. Time t
PHQV
is
required after return from reset mode until initial
memory access outputs are valid. After this wake-
up interval, normal operation is restored. The CUI is
reset to read array mode and status register is set
to 80H.
During
configuration modes, RP#-low will abort the
operation. In default mode, STS transitions low and
remains low for a maximum time of t
PLPH
+ t
PHRH
until the reset operation is complete. Memory
contents being altered are no longer valid; the data
may be partially corrupted after a program or
partially altered after an erase or lock-bit
configuration. Time t
PHWL
is required after RP#
goes to logic-high (V
IH
) before another command
can be written.
block
erase,
program,
or
lock-bit
As with any automated device, it is important to
assert RP# during system reset. When the system
comes out of reset, it expects to read from the flash
memory. Automated flash memories provide status
information when accessed during block erase,
program, or lock-bit configuration modes. If a CPU
reset occurs with no flash memory reset, proper
initialization may not occur because the flash
memory may be providing status information
instead of array data. Intel’s flash memories allow
proper initialization following a system reset through
the use of the RP# input. In this application, RP# is
controlled by the same RESET# signal that resets
the system CPU.
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