參數(shù)資料
型號(hào): 28F640J5
英文描述: Dual-Slot, PCMCIA Analog Power Controller
中文描述: 28F640J5 -英特爾StrataFlash內(nèi)存技術(shù),32和64兆比特
文件頁數(shù): 24/53頁
文件大?。?/td> 306K
代理商: 28F640J5
INTEL
StrataFlash MEMORY TECHNOLOGY, 32 AND 64 MBIT
E
DEVICE GEOMETRY DEFINITION
24
PRELIMINARY
4.2.6
This field provides critical details of the flash device geometry.
Table 11. Device Geometry Definition
Offset
Length
(bytes)
Description
Intel
StrataFlash
Memory
27h
01h
Device Size = 2
N
in number of bytes.
27:
0017h
(64-Mbit)
27:
0016h
(32-Mbit)
28h
02h
Flash Device Interface description
value
meaning
0000h
0002h
x8 asynchronous
x8/x16 asynchronous
28:
29:
0002h
0000h
2Ah
02h
Maximum number of bytes in write buffer = 2
N
2A:
2B:
0005h
0000h
2Ch
01h
Number of Erase Block Regions within device:
bits 7–0 = x
= # of Erase Block Regions
2C:
0001h
2Dh
04h
Erase Block Region Information
bits 15–0 = y
, where y+1 = Number of Erase Blocks
of identical size within region
bits 31–16 = z
, where the Erase Block(s) within this
Region are (z) times 256 bytes
y: 64 Blocks
(64-Mbit)
2D:
2E:
003Fh
0000h
y: 32 Blocks
(32-Mbit)
2D:
2E:
001Fh
0000h
z: (128 KB size)
2F:
0000h
30:
0002h
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