參數(shù)資料
型號(hào): 28F640J5
英文描述: Dual-Slot, PCMCIA Analog Power Controller
中文描述: 28F640J5 -英特爾StrataFlash內(nèi)存技術(shù),32和64兆比特
文件頁數(shù): 45/53頁
文件大?。?/td> 306K
代理商: 28F640J5
E
INTEL
StrataFlash MEMORY TECHNOLOGY, 32 AND 64 MBIT
45
PRELIMINARY
Output
0.8
Test Points
Input
2.0
2.0
0.8
2.4
0.45
AC test inputs are driven at V
(2.4 V
) for a Logic "1" and V
(0.45 V
) for a Logic "0." Input timing begins at V
IH
(2.0 V
TTL
) and V
IL
(0.8 V
TTL
). Output timing ends at V
IH
and V
IL
. Input rise and fall times (10% to 90%) <10 ns.
Figure 13. Transient Input/Output Reference Waveform for V
CCQ
= 5.0 V ± 10%
(Standard Testing Configuration)
Output
Test Points
Input
1.35
2.7
0.0
1.35
AC test inputs are driven at 2.7V for a Logic "1" and 0.0V for a Logic "0." Input timing begins, and output timing ends, at 1.35 V
(50% of V
CCQ
). Input rise and fall times (10% to 90%) <10 ns.
Figure 14. Transient Input/Output Reference Waveform for V
CCQ
= 2.7 V
3.6 V
Device
Under Test
Out
R
L
= 3.3 k
1N914
1.3V
C
L
NOTE:
C
L
Includes Jig Capacitance
Figure 15. Transient Equivalent Testing
Load Circuit
Test Configuration Capacitance Loading Value
Test Configuration
C
L
(pF)
V
CCQ
= 5.0 V
±
10%
100
V
CCQ
= 2.7 V
3.6 V
50
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參數(shù)描述
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