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參數(shù)資料
| 型號(hào)： | 28F640J5 |
| 英文描述： | Dual-Slot, PCMCIA Analog Power Controller |
| 中文描述： | 28F640J5 -英特爾StrataFlash內(nèi)存技術(shù)，32和64兆比特 |
| 文件頁數(shù)： | 14/53頁 |
| 文件大?。?/td> | 306K |
| 代理商： | 28F640J5 |
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INTEL
StrataFlash MEMORY TECHNOLOGY, 32 AND 64 MBIT
E
Read Query
V
PEN
additionally enables block erase, program,
and lock-bit configuration operations.
14
PRELIMINARY
3.5
The read query operation outputs block status
information, CFI (Common Flash Interface) ID
string,
system
interface
geometry information, and Intel-specific extended
query information.
information,
device
3.6
Read Identifier Codes
The read identifier codes operation outputs the
manufacturer code, device code, block lock
configuration codes for each block, and the master
lock configuration code (see Figure 6). Using the
manufacturer and device codes, the system CPU
can automatically match the device with its proper
algorithms. The block lock and master lock
configuration codes identify locked and unlocked
blocks and master lock-bit setting.
3.7
Write
Writing commands to the CUI enables reading of
device data, query, identifier codes, inspection and
clearing of the status register, and, when V
PEN
=
V
PENH
, block erasure, program, and lock-bit
configuration.
The Block Erase command requires appropriate
command data and an address within the block to
be erased. The Byte/Word Program command
requires the command and address of the location
to be written. Set Master and Block Lock-Bit
commands require the command and address
within the device (Master Lock) or block within the
device (Block Lock) to be locked. The Clear Block
Lock-Bits command requires the command and
address within the device.
The CUI does not occupy an addressable memory
location. It is written when the device is enabled
and WE# is active. The address and data needed to
execute a command are latched on the rising edge
of WE# or the first edge of CE
0
, CE
1
, or CE
2
that
disables the device (see Table 2, Chip Enable Truth
Table). Standard microprocessor write timings are
used.
4.0 COMMAND DEFINITIONS
When the V
PEN
voltage
≤
V
PENLK
, only read
operations from the status register, query, identifier
codes, or blocks are enabled. Placing V
PENH
on
Device operations are selected by writing specific
commands into the CUI. Table 4 defines these
commands.
Reserved for Future
Implementation
Reserved for Future
Implementation
(Blocks 32 through 62)
Reserved for Future
Implementation
Reserved for Future
Implementation
(Blocks 2 through 30)
Reserved for Future
Implementation
Reserved for Future
Implementation
Block 63
Block 31
Block 1
Block 0 Lock Configuration
Device Code
Reserved for Future
Implementation
Block 0
Master Lock Configuration
Manufacturer Code
3FFFFF
3F0003
3F0002
3F0000
3EFFFF
1EFFFF
1F0003
1F0002
1F0000
01FFFF
010003
010002
010000
00FFFF
000004
000003
000002
000001
000000
3
6
Word
Address
A[22-1]: 64 Mbit
A[21-1]: 32 Mbit
Block 31 Lock Configuration
Block 63 Lock Configuration
Block 1 Lock Configuration
0606_06
NOTE:
A
is not used in either x8 or x16 modes when obtaining
these identifier codes. Data is always given on the low byte
in x16 mode (upper byte contains 00h).
Figure 6. Device Identifier Code Memory Map
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 28F640L18 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:StrataFlash Wireless Memory |
| 28F640L30 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:1.8 Volt Intel StrataFlash㈢ Wireless Memory with 3.0-Volt I/O (L30) |
| 28F640P3 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel StrataFlash Embedded Memory |
| 28F640W30 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:1.8 Volt Intel Wireless Flash Memory with 3 Volt I/O and SRAM (W30) |
| 28F650 | 制造商:Cinch Connectors 功能描述:1 Lug Terminal Strip |
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