參數(shù)資料
型號: XRT86VL30IV-F
廠商: Exar Corporation
文件頁數(shù): 9/175頁
文件大?。?/td> 0K
描述: IC FRAMR/LIU T1/E1/J1 QD 128LQFP
標(biāo)準(zhǔn)包裝: 72
控制器類型: T1/E1/J1 調(diào)幀器,LIU
電源電壓: 3.3V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 128-LQFP
供應(yīng)商設(shè)備封裝: 128-LQFP(14x20)
包裝: 托盤
其它名稱: 1016-1485
XRT86VL30IV-F-ND
XRT86VL30
101
SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
REV. 1.0.1
2
SLIP
RO
0
Slip Buffer Block Interrupt Status
This bit indicates whether or not the Slip Buffer block has any out-
standing interrupt request awaiting service.
0 = Indicates no outstanding Slip Buffer Block interrupt request is
awaiting service
1 = Indicates Slip Buffer block has an interrupt request awaiting ser-
vice. Interrupt Service routine should branch to the interrupt source
and read the Slip Buffer Interrupt Status register (address 0x0B08)
to clear the interrupt
NOTE:
This bit will be reset to 0 after the microprocessor has
performed a read to the Slip Buffer Interrupt Status
Register.
1
ALARM
RO
0
Alarm & Error Block Interrupt Status
This bit indicates whether or not the Alarm & Error Block has any
outstanding interrupt request awaiting service.
0 = Indicates no outstanding interrupt request is awaiting service
1 = Indicates the Alarm & Error Block has an interrupt request await-
ing service. Interrupt service routine should branch to the interrupt
source and read the corresponding alarm and error status registers
(address 0x0B02, 0x0B0E, 0x0B40) to clear the interrupt.
NOTE:
This bit will be reset to 0 after the microprocessor has
performed a read to the corresponding Alarm & Error
Interrupt Status register that generated the interrupt.
0
T1 FRAME
RO
0
T1 Framer Block Interrupt Status
This bit indicates whether or not the T1 Framer block has any out-
standing interrupt request awaiting service.
0 = Indicates no outstanding interrupt request is awaiting service.
1 = Indicates the T1 Framer Block has an interrupt request awaiting
service. Interrupt service routine should branch to the interrupt
source and read the T1 Framer status register (address 0x0B04) to
clear the interrupt
NOTE:
This bit will be reset to 0 after the microprocessor has
performed a read to the T1 Framer Interrupt Status register.
TABLE 94: BLOCK INTERRUPT STATUS REGISTER (BISR)
HEX ADDRESS: 0X0B00
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
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參數(shù)描述
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