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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | XRT86VL30IV-F |
| 寤犲晢锛� | Exar Corporation |
| 鏂囦欢闋�(y猫)鏁�(sh霉)锛� | 72/175闋�(y猫) |
| 鏂囦欢澶у皬锛� | 0K |
| 鎻忚堪锛� | IC FRAMR/LIU T1/E1/J1 QD 128LQFP |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 72 |
| 鎺у埗鍣ㄩ鍨嬶細 | T1/E1/J1 瑾�(di脿o)骞€鍣�锛孡IU |
| 闆绘簮闆诲锛� | 3.3V |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 128-LQFP |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 128-LQFP锛�14x20锛� |
| 鍖呰锛� | 鎵樼洡(p谩n) |
| 鍏跺畠鍚嶇ū锛� | 1016-1485 XRT86VL30IV-F-ND |
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XRT86VL30
158
REV. 1.0.1
SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
TABLE 134: LIU CHANNEL CONTROL CABLE LOSS REGISTER (LIUCCCCR)
HEX ADDRESS: 0X0F07
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
7
Reserved
RO
0
6
Reserved
RO
0
5-0
CLOS[5:0]
RO
0
Cable Loss [5:0]:
These bits represent the six bit receive selective equalizer setting
which is also a binary word that represents the cable attenuation
indication within 卤1dB.
CLOS5_n is the most significant bit (MSB) and CLOS0_n is the
least significant bit (LSB).
NOTE: In RxSYNC (Sect 13) mode, ExLOS must be configured (this
will set the DLOS to 4,096 bits which does not meet G.775).
However, the CLOS bits can be used to meet the DLOS
requirements of G.775 with a simple software procedure. To
meet G.775, simply choose a desired value of attenuation
(For example: 12dB) to monitor in this register for RLOS
within a time period of 175 Clock Cycles +/-75. The internal
RLOS alarm should be masked unless ExLOS is being
used. For more details, please contact the factory.
TABLE 135: LIU CHANNEL CONTROL ARBITRARY REGISTER 1 (LIUCCAR1)
HEX ADDRESS: 0X0F08
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
7
Reserved
R/W
0
6-0
Arb_Seg1
R/W
0
Arbitrary Transmit Pulse Shape, Segment 1:
These seven bits form the first of the eight segments of the transmit
shape pulse when the XRT86VL30 is configured in 鈥淎rbitrary Mode鈥�.
These seven bits represent the amplitude of the nth channel's arbi-
trary pulse in signed magnitude format with Bit 6 as the sign bit and
Bit 0 as the least significant bit (LSB).
NOTE: Arbitrary mode is enabled by writing to the EQC[4:0] bits in
register 0x0F00.
TABLE 136: LIU CHANNEL CONTROL ARBITRARY REGISTER 2 (LIUCCAR2)
HEX ADDRESS: 0X0F09
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
7
Reserved
R/W
0
6-0
Arb_Seg2
R/W
0
Arbitrary Transmit Pulse Shape, Segment 2
These seven bits form the second of the eight segments of the
transmit shape pulse when the XRT86VL30 is configured in 鈥淎rbi-
trary Mode鈥�.
These seven bits represent the amplitude of the nth channel's arbi-
trary pulse in signed magnitude format with Bit 6 as the sign bit and
Bit 0 as the least significant bit (LSB).
NOTE: Arbitrary mode is enabled by writing to the EQC[4:0] bits in
register 0x0F00.
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| XRT86VL32IB-F | IC LIU/FRAMER T1/E1/J1 2CH 225BG |
| XRT86VL34IB-F | IC LIU/FRAMER T1/E1/J1 4CH 225BG |
| XRT86VL38IB484-F | IC LIU/FRAMER T1/E1/J1 8CH 484BG |
| XRT86VX38IB329-F | IC TI/E1/J1 FRAMER/LIU 329FPBGA |
| XRT94L31IB-L | IC MAPPER DS3/E3/STS-1 504TBGA |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| XRT86VL30IV-F | 鍒堕€犲晢:Exar Corporation 鍔熻兘鎻忚堪:T1/E1 Framer Combo IC |
| XRT86VL32 | 鍒堕€犲晢:EXAR 鍒堕€犲晢鍏ㄧū:EXAR 鍔熻兘鎻忚堪:DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION |
| XRT86VL32_07 | 鍒堕€犲晢:EXAR 鍒堕€犲晢鍏ㄧū:EXAR 鍔熻兘鎻忚堪:DUAL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION |
| XRT86VL32_0709 | 鍒堕€犲晢:EXAR 鍒堕€犲晢鍏ㄧū:EXAR 鍔熻兘鎻忚堪:DUAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION |
| XRT86VL32_1 | 鍒堕€犲晢:EXAR 鍒堕€犲晢鍏ㄧū:EXAR 鍔熻兘鎻忚堪:DUAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION |
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