參數(shù)資料
型號： XRT86VL30IV-F
廠商： Exar Corporation
文件頁數(shù)： 37/175頁
文件大?。?/td> 0K
描述： IC FRAMR/LIU T1/E1/J1 QD 128LQFP
標(biāo)準(zhǔn)包裝： 72
控制器類型： T1/E1/J1 調(diào)幀器，LIU
電源電壓： 3.3V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 128-LQFP
供應(yīng)商設(shè)備封裝： 128-LQFP（14x20）
包裝： 托盤
其它名稱： 1016-1485
XRT86VL30IV-F-ND
XRT86VL30
126
REV. 1.0.1
SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
3
RxEOT
RUR/
WC
0
Receive HDLC2 Controller End of Reception (RxEOT) Interrupt
Status
This Reset-Upon-Read bit indicates whether or not the Receive
HDLC2 Controller End of Reception (RxEOT) Interrupt has occurred
since the last read of this register. Receive HDLC2 Controller will
declare this interrupt once it has completely received a full data link
message, or once the buffer is full.
0 = Receive HDLC2 Controller End of Reception (RxEOT) interrupt
has not occurred since the last read of this register
1 = Receive HDLC2 Controller End of Reception (RxEOT) Interrupt
has occurred since the last read of this register
2
FCS Error
RUR/
WC
0
FCS Error Interrupt Status
This Reset-Upon-Read bit indicates whether or not the FCS Error
Interrupt has occurred since the last read of this register. Receive
HDLC2 Controller will declare this interrupt when it has detected the
FCS error in the most recently received data link message.
0 = FCS Error interrupt has not occurred since the last read of this
register
1 = FCS Error interrupt has occurred since the last read of this regis-
ter
1
Rx ABORT
RUR/
WC
0
Receipt of Abort Sequence Interrupt Status
This Reset-Upon-Read bit indicates whether or not the Receipt of
Abort Sequence interrupt has occurred since last read of this regis-
ter. Receive HDLC2 Controller will declare this interrupt if it detects
the Abort Sequence (i.e. a string of seven (7) consecutive 1’s) in the
incoming data link channel.
0 = Receipt of Abort Sequence interrupt has not occurred since last
read of this register
1 = Receipt of Abort Sequence interrupt has occurred since last
read of this register
0
RxIDLE
RUR/
WC
0
Receipt of Idle Sequence Interrupt Status
This Reset-Upon-Read bit indicates whether or not the Receipt of
Idle Sequence interrupt has occurred since the last read of this reg-
ister. The Receive HDLC2 Controller will declare this interrupt if it
detects the flag sequence octet (0x7E) in the incoming data link
channel. If RxIDLE "AND" RxEOT occur together, then the entire
HDLC message has been received.
0 = Receipt of Idle Sequence interrupt has not occurred since last
read of this register
1 = Receipt of Idle Sequence interrupt has occurred since last read
of this register.
TABLE 112: DATA LINK STATUS REGISTER 2 (DLSR2)
HEX ADDRESS: 0X0B16
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
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