TABLE
參數(shù)資料
型號： XRT86VL30IV-F
廠商： Exar Corporation
文件頁數(shù)： 103/175頁
文件大?。?/td> 0K
描述： IC FRAMR/LIU T1/E1/J1 QD 128LQFP
標準包裝： 72
控制器類型： T1/E1/J1 調(diào)幀器，LIU
電源電壓： 3.3V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 128-LQFP
供應商設備封裝： 128-LQFP（14x20）
包裝： 托盤
其它名稱： 1016-1485
XRT86VL30IV-F-ND
XRT86VL30
28
REV. 1.0.1
SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
TABLE 13: RECEIVE SIGNALING CHANGE REGISTER 0 (RSCR 0)
HEX ADDRESS: 0X010D
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
7
Ch. 0
RUR
0
These bits indicate whether the Channel Associated signaling data,
associated with Time-Slots 0 through 7 within the incoming T1 data-
stream, has changed since the last read of this register, as depicted
below.
0 - CAS data (for Time-slots 0 through 7) has NOT changed since the
last read of this register.
1 - CAS data (for Time-slots 0 through 7) HAS changed since the last
read of this register.
NOTES: This register is only active if the incoming T1 data-stream is
using Channel Associated Signaling.
6
Ch. 1
RUR
0
5
Ch.2
RUR
0
4
Ch.3
RUR
0
3
Ch.4
RUR
0
2
Ch.5
RUR
0
1
Ch.6
RUR
0
Ch.7
RUR
0
TABLE 14: RECEIVE SIGNALING CHANGE REGISTER 1(RSCR 1)
HEX ADDRESS: 0X010E
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
7
Ch.8
RUR
0
These bits indicate whether the Channel Associated signaling data,
associated with Time-Slots 8 through 15 within the incoming T1 data-
stream, has changed since the last read of this register, as depicted
below.
0 - CAS data (for Time-slots 8 through 15) has NOT changed since the
last read of this register.
1 - CAS data (for Time-slots 8 through 15) HAS changed since the last
read of this register.
This register is only active if the incoming T1 data-stream is using
Channel Associated Signaling.
6
Ch.9
RUR
0
5
Ch.10
RUR
0
4
Ch.11
RUR
0
3
Ch.12
RUR
0
2
Ch.13
RUR
0
1
Ch.14
RUR
0
Ch.15
RUR
0
TABLE 15: RECEIVE SIGNALING CHANGE REGISTER 2 (RSCR 2)
HEX ADDRESS: 0X010F
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
7
Ch.16
RUR
0
These bits indicate whether the Channel Associated signaling data, associ-
ated with Time-Slots 16 through 23 within the incoming T1 data-stream, has
changed since the last read of this register, as depicted below.
0 - CAS data (for Time-slots 16 through 23) has NOT changed since the last
read of this register.
1 - CAS data (for Time-slots 16 through 23) HAS changed since the last read
of this register.
NOTE:
This register is only active if the incoming T1 data-stream is using
Channel Associated Signaling.
6
Ch.17
RUR
0
5
Ch.18
RUR
0
4
Ch.19
RUR
0
3
Ch.20
RUR
0
2
Ch.21
RUR
0
1
Ch.22
RUR
0
Ch.23
RUR
0
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