
XRT84L38
407
REV. 1.0.1
OCTAL T1/E1/J1 FRAMER
next WRITE access to the LAPD Buffer indirect data register will be direct to location 1 within the transmit data
link buffer and so on, until all 96 bytes of the transmit buffer is filled.
For example, if the first byte of the SLC96 Data Link message to be sent is (101011) and the next available
transmit data link buffer of Channel n is 1. The user should write pattern (00101011) into transmit data link
buffer 1 of Channel n. The following microprocessor access to the framer should be done:
WR
n7H
2BH
The first byte of the SLC96 Data Link message is written into location 0 of the transmit data link buffer. If the
next byte of the data link message is (101001), the user should perform another microprocessor WRITE
access of pattern (00101001):
WR
n7H
29H
The second byte of data link message is written into location 1 of the transmit data link buffer. The WRITE
access should be repeated until all six bytes of SLC96 Data Link message is written into the transmit buffer or
the transmit buffer is completely filled.
13.1.5.1.3
Step 3: Enable transmit data link message interrupt
The SLC96 Data Link Controller can generate the Transmit Start of Transfer (TxSOT) interrupt indicating the
status of data link message transmission to the microprocessor. To enable this interrupt, the Transmit Start of
Transfer Enable bit of the Data Link Interrupt Enable Register (DLIER) have to be set. In addition, the HDLC
Controller Interrupt Enable bit of the Block Interrupt Enable Register (BIER) needs to be one.
The table below shows configurations of the Transmit Start of Transfer Enable bit of the Data Link Interrupt
Enable Register.
DATA LINK INTERRUPT ENABLE REGISTER (DLIER) (INDIRECT ADDRESS = 0XNAH, 0X07H)
The table below shows configurations of the HDLC Controller Interrupt Enable bit of the Block Interrupt Enable
Register.
BLOCK INTERRUPT ENABLE REGISTER (BIER) (INDIRECT ADDRESS = 0XNAH, 0X00H)
When this interrupt enable bit is set and the SLC96 Data Link message is transmitted to the data link
channel, the SLC96 Data Link Controller changes the Transmit Start of Transfer status bits of the Data Link
Status Register (DLSR). This status indicator is valid until the Data Link Status Register is read. Reading this
register clears the associated interrupt if Reset Upon Read is selected in Interrupt Control Register (ICR).
Otherwise, a write-to-clear operation by the microprocessor is required to reset these status indicators.
B
IT
N
UMBER
B
IT
N
AME
B
IT
T
YPE
B
IT
D
ESCRIPTION
6
Transmit Start of
Transfer Enable
R/W
0 - The Transmit Start of Transfer interrupt is disabled.
1 - The Transmit Start of Transfer interrupt is enabled.
B
IT
N
UMBER
B
IT
N
AME
B
IT
T
YPE
B
IT
D
ESCRIPTION
3
HDLC Controller
Interrupt Enable
R/W
0 - Every interrupt generated by the HDLC Controller is disabled.
1 - Every interrupt generated by the HDLC Controller is enabled.