
XRT84L38
355
REV. 1.0.1
OCTAL T1/E1/J1 FRAMER
11.2.5
How to configure the framer to input CRC-4 bits from different sources
Each E1 CRC-4 multi-frame is divided into two sub-multi-frames. Each sub-multi-frame consists of 8 E1
frames. If the framer is configured to operate in CRC-4 multi-frame format, bit 1 of the FAS frames are used as
Cyclic Redundancy Check (CRC-4) code of the last CRC-4 sub- multi-frame. The CRC-4 bits are an indicator
of the link quality and could be monitored by the user to establish error performance report.
The XRT84L38 can generate the CRC-4 bits internally by calculating the CRC check-sum of all the payload
bits in each E1 sub-multi-frame.
At the same time, the users can generate the CRC-4 bits externally and insert them into the framer through the
Transmit Serial Data Input Interface block via the TxSer_n pin. It is the user's responsibility to correctly
compute the CRC-4 bits according to E1 algorithm. Also, the user has to make sure that the CRC-4 bits are
inserted into the framer at right position and right timing. However, this option is only available when the
XRT84L38 is configured to run at a normal back-plane rate of 2.048Mbit/s.
The CRC-4 Source Select bit of the Synchronization MUX Register (SMR) controls from where to input CRC-4
bits into the framer. The table below shows configurations of the CRC-4 Source Select bit of the
Synchronization MUX Register (SMR).
SYNCHRONIZATION MUX REGISTER (SMR) (INDIRECT ADDRESS = 0XN0H, 0X09H)
11.2.6
How to configure the framer to input E bits from different sources
Each E1 CRC-4 multi-frame is divided into two sub-multi-frames. Each sub-multi-frame consists of 8 E1
frames, 4 of them are FAS frames and the other 4 are non-FAS frames. Of the second CRC-4 sub-multi-frame,
bit 1 of the last 2 non-FAS frames is called E bit.
The E bits are used to indicate that the previous received sub-multi-frame is error-ed. When a sub-multi-frame
is received, the framer calculated the CRC-4 bits of the received sub-multi-frame. The frame then compares
the calculated CRC-4 bits with the received CRC-4 bits. If they are the same, the framer will set E bit to "1" and
transmit it to the remote terminal. If the calculated CRC-4 bits and the receive CRC-4 bits are different, the
framer will set E bit to "0" and transmit it out. The first E bit indicates error of the first CRC-4 sub-multi-frame
while the second E bit indicates error of the second CRC-4 sub-multi-frame.
The delay between the detection of an error-ed CRC-4 sub-multi-frame and the setting of the corresponding E
bit that represents the error state should not be more than one second. If the E bits are not used, they should
be set to "1".
N
OTE
:
The E bits will always be taken into account even if the sub-multi-frame which contains them is error-ed.
Under default condition, the XRT84L38 generate the E bits internally by calculating the CRC check-sum of all
the payload bits in each received E1 sub-multi-frame and compare them against the received CRC-4 bits.
At the same time, the users can force the E bits to either "0" or "1". Source of the E bits can also be the internal
HDLC controller such that the E bits can be used to transmit data link message.
B
IT
N
UMBER
B
IT
N
AME
B
IT
T
YPE
B
IT
D
ESCRIPTION
1
CRC-4 Source
Select
R/W
This READ/WRITE bit-field permits the user to determine where the CRC-
4 bits should be inserted.
0 - The CRC-4 bits are generated and inserted by the framer internally.
1 - If the framer is operating in normal 2.048Mbit/s mode, the CRC-4 bits
are generated by external equipment and passed through from the Trans-
mit Serial Data Input Interface block via the TxSer_n pin.