
XRT84L38
389
REV. 1.0.1
OCTAL T1/E1/J1 FRAMER
The table below shows configurations of the Receive Bipolar Violation Interrupt Enable bit of the Alarm and
Error Interrupt Enable Register (AEIER).
ALARM AND ERROR INTERRUPT ENABLE REGISTER (AEIER) (INDIRECT ADDRESS = 0XNAH,
0X03H)
The table below shows configurations of the Alarm and Error Interrupt Enable bit of the Block Interrupt Enable
Register.
BLOCK INTERRUPT ENABLE REGISTER (BIER) (INDIRECT ADDRESS = 0XNAH, 0X01H)
When these interrupt enable bits are set and one or more Bipolar Violations are present in the incoming E1
frame, the XRT84L38 framer will declare Receive Bipolar Violation by doing the following:
Set the Receive Bipolar Violation bit of the Alarm and Error Status Register to one indicating there are one or
more Bipolar Violations. This status indicator is valid until the Framer Interrupt Status Register is read.
Reading this register clears the associated interrupt if Reset-Upon-Read is selected in Interrupt Control
Register (ICR). Otherwise, a write-to-clear operation by the microprocessor is required to reset these status
indicators.
The table below shows the Receive Bipolar Violation status bits of the Alarm and Error Status Register.
ALARM AND ERROR STATUS REGISTER (AESR) (INDIRECT ADDRESS = 0XNAH, 0X02H)
12.5.6
How to configure the framer to detect Loss of Signal
A Loss of Signal or LOS occurs when neither RPOS nor RNEG inputs of the framer receives a high level input
for 32 consecutive bit times. The Alarm indication logic within the Receive Framer block of the XRT84L38
framer monitors the incoming E1 frames for Loss of Signal conditions. If used in conjunction with EXAR LIUs,
for example, the XRT83L3x family, the XRT84L38 framer also declares LOS when the Receive LOS (RxLOS)
input pin is pulled HIGH.
The removal of LOS condition is through detection of 12.5% ones over 32 consecutive bits. In the other words,
XRT84L38 framer will remove LOS alarm when there is no 4 consecutive zeros received.
N
OTE
:
The implementation of LOS detection and removal only apply to B8ZS coded bipolar inputs.
B
IT
N
UMBER
B
IT
N
AME
B
IT
T
YPE
B
IT
D
ESCRIPTION
3
Receive Bipolar
Violation Interrupt
Enable
R/W
0 - The Receive Bipolar Violation interrupt is disabled. Occurrence of one
or more bipolar violations will not generate an interrupt.
1 - The Receive Bipolar Violation interrupt is enabled. Occurrence of one
or more bipolar violations will generate an interrupt.
B
IT
N
UMBER
B
IT
N
AME
B
IT
T
YPE
B
IT
D
ESCRIPTION
1
Alarm and Error
Interrupt Enable
R/W
0 - Every interrupt generated by the Alarm and Error Interrupt Status Reg-
ister (AEISR) is disabled.
1 - Every interrupt generated by the Alarm and Error Interrupt Status Reg-
ister (AEISR) is enabled.
B
IT
N
UMBER
B
IT
N
AME
B
IT
T
YPE
B
IT
D
ESCRIPTION
3
Receive Bipolar
Violation State
Change
RUR /
WC
0 - There is no change of Bipolar Violation state in the incoming E1 pay-
load data.
1 - There is change of Bipolar Violation state in the incoming E1 payload
data.