
XRT84L38
XIV
OCTAL T1/E1/J1 FRAMER
REV. 1.0.1
13.2.4.1 H
OW
TO
CONFIGURE
THE
R
ECEIVE
HDLC C
ONTROLLER
B
LOCK
TO
RECEIVE
MOS
MESSAGE
............................. 415
D
ATA
L
INK
I
NTERRUPT
E
NABLE
R
EGISTER
(DLIER) (I
NDIRECT
A
DDRESS
= 0
XN
AH, 0
X
07H) ...................... 415
B
LOCK
I
NTERRUPT
E
NABLE
R
EGISTER
(BIER) (I
NDIRECT
A
DDRESS
= 0
XN
AH, 0
X
00H) .............................. 416
D
ATA
L
INK
S
TATUS
R
EGISTER
(DLSR) (I
NDIRECT
A
DDRESS
= 0
XN
AH, 0
X
06H)......................................... 416
D
ATA
L
INK
I
NTERRUPT
E
NABLE
R
EGISTER
(DLIER) (I
NDIRECT
A
DDRESS
= 0
XN
AH, 0
X
07H) ...................... 416
D
ATA
L
INK
S
TATUS
R
EGISTER
(DLSR) (I
NDIRECT
A
DDRESS
= 0
XN
AH, 0
X
06H)......................................... 417
D
ATA
L
INK
I
NTERRUPT
E
NABLE
R
EGISTER
(DLIER) (I
NDIRECT
A
DDRESS
= 0
XN
AH, 0
X
07H) ...................... 417
D
ATA
L
INK
S
TATUS
R
EGISTER
(DLSR) (I
NDIRECT
A
DDRESS
= 0
XN
AH, 0
X
06H)......................................... 417
R
ECEIVE
D
ATA
L
INK
B
YTE
C
OUNT
R
EGISTER
(RDLBCR) (I
NDIRECT
A
DDRESS
= 0
XN
0H, 0
X
15H).............. 418
R
ECEIVE
D
ATA
L
INK
B
YTE
C
OUNT
R
EGISTER
(RDLBCR) (I
NDIRECT
A
DDRESS
= 0
XN
0H, 0
X
15H).............. 418
D
ATA
L
INK
S
TATUS
R
EGISTER
(DLSR) (I
NDIRECT
A
DDRESS
= 0
XN
AH, 0
X
06H)......................................... 418
13.2.5 RECEIVE SLC96 DATA LINK CONTROLLER...................................................................................................... 419
R
ECEIVE
SLC96 M
ESSAGE
R
EGISTERS
.................................................................................................. 419
13.2.5.1 H
OW
TO
CONFIGURE
THE
SLC96 D
ATA
L
INK
C
ONTROLLER
TO
RECEIVE
SLC96 D
ATA
L
INK
M
ESSAGES
....... 419
D
ATA
L
INK
I
NTERRUPT
E
NABLE
R
EGISTER
(DLIER) (I
NDIRECT
A
DDRESS
= 0
XN
AH, 0
X
07H) ...................... 420
B
LOCK
I
NTERRUPT
E
NABLE
R
EGISTER
(BIER) (I
NDIRECT
A
DDRESS
= 0
XN
AH, 0
X
00H) .............................. 420
D
ATA
L
INK
S
TATUS
R
EGISTER
(DLSR) (I
NDIRECT
A
DDRESS
= 0
XN
AH, 0
X
06H).......................................... 420
D
ATA
L
INK
I
NTERRUPT
E
NABLE
R
EGISTER
(DLIER) (I
NDIRECT
A
DDRESS
= 0
XN
AH, 0
X
07H) ...................... 421
D
ATA
L
INK
S
TATUS
R
EGISTER
(DLSR) (I
NDIRECT
A
DDRESS
= 0
XN
AH, 0
X
06H)......................................... 421
R
ECEIVE
D
ATA
L
INK
B
YTE
C
OUNT
R
EGISTER
(RDLBCR) (I
NDIRECT
A
DDRESS
= 0
XN
0H, 0
X
15H).............. 421
14.0 E1 HDLC CONTROLLER BLOCK..................................................................................................... 423
14.1 E1 TRANSMIT HDLC CONTROLLER BLOCK............................................................................................. 423
14.1.1 DESCRIPTION OF THE E1 TRANSMIT HDLC CONTROLLER BLOCK ................................................................ 423
S
YNCHRONIZATION
MUX R
EGISTER
(SMR) (I
NDIRECT
A
DDRESS
= 0
XN
0H, 0
X
09H) .................................. 423
D
ATA
L
INK
C
ONTROL
R
EGISTER
(DLCR) (I
NDIRECT
A
DDRESS
= 0
XN
0H, 0
X
13H) ...................................... 424
14.1.2 HOW TO CONFIGURE XRT84L38 TO TRANSMIT DATA LINK INFORMATION THROUGH THE NATIONAL BITS (SA4
THROUGH SA8)........................................................................................................................................................... 424
T
RANSMIT
S
IGNALING
AND
D
ATA
L
INK
S
ELECT
R
EGISTER
(TSDLSR) (I
NDIRECT
A
DDRESS
= 0
XN
0H, 0
X
0AH) 424
T
RANSMIT
S
IGNALING
AND
D
ATA
L
INK
S
ELECT
R
EGISTER
(TSDLSR) (I
NDIRECT
A
DDRESS
= 0
XN
0H, 0
X
0AH) 425
14.1.3 HOW TO CONFIGURE XRT84L38 TO TRANSMIT DATA LINK INFORMATION THROUGH TIMESLOT 16 OCTET 425
T
RANSMIT
S
IGNALING
AND
D
ATA
L
INK
S
ELECT
R
EGISTER
(TSDLSR) (I
NDIRECT
A
DDRESS
= 0
XN
0H, 0
X
0AH) 425
14.1.4 HOW TO CONFIGURE XRT84L38 TO TRANSMIT DATA LINK INFORMATION THROUGH D OR E CHANNELS 425
T
RANSMIT
C
HANNEL
C
ONTROL
R
EGISTER
(TCCR) (I
NDIRECT
A
DDRESS
= 0
XN
2H, 0
X
00H - 0
X
1FH).......... 426
14.1.5 TRANSMIT BOS (BIT ORIENTED SIGNALING) PROCESSOR.............................................................................. 426
14.1.6 TRANSMIT MOS (MESSAGE ORIENTED SIGNALING) OR LAPD CONTROLLER.............................................. 426
14.2 E1 RECEIVE HDLC CONTROLLER BLOCK................................................................................................ 426
14.2.1 DESCRIPTION OF THE E1 RECEIVE HDLC CONTROLLER BLOCK ................................................................... 426
D
ATA
L
INK
S
TATUS
R
EGISTER
(DLSR) (I
NDIRECT
A
DDRESS
= 0
XN
AH, 0
X
06H)......................................... 427
14.2.2 HOW TO CONFIGURE XRT84L38 TO RECEIVE DATA LINK INFORMATION THROUGH THE NATIONAL BITS (SA4
THROUGH SA8)........................................................................................................................................................... 427
R
ECEIVE
S
IGNALING
AND
D
ATA
L
INK
S
ELECT
R
EGISTER
(RSDLSR) (I
NDIRECT
A
DDRESS
= 0
XN
0H, 0
X
0CH) 428
R
ECEIVE
S
IGNALING
AND
D
ATA
L
INK
S
ELECT
R
EGISTER
(RSDLSR) (I
NDIRECT
A
DDRESS
= 0
XN
0H, 0
X
0CH) 428
14.2.3 HOW TO CONFIGURE XRT84L38 TO RECEIVE DATA LINK INFORMATION THROUGH TIMESLOT 16 OCTET 428
R
ECEIVE
S
IGNALING
AND
D
ATA
L
INK
S
ELECT
R
EGISTER
(RSDLSR) (I
NDIRECT
A
DDRESS
= 0
XN
0H, 0
X
0CH) 429
14.2.4 HOW TO CONFIGURE XRT84L38 TO RECEIVE DATA LINK INFORMATION THROUGH D OR E CHANNELS 429
R
ECEIVE
C
HANNEL
C
ONTROL
R
EGISTER
(RCCR) (I
NDIRECT
A
DDRESS
= 0
XN
2H, 0
X
60H - 0
X
7FH) ........... 429
14.2.5 RECEIVE BOS (BIT ORIENTED SIGNALING) PROCESSOR................................................................................. 429
14.2.6 RECEIVE LAPD CONTROLLER .............................................................................................................................. 429
15.0 TRANSMIT LIU INTERFACE............................................................................................................. 431
16.0 RECEIVE LIU INTERFACE................................................................................................................ 431
ORDERING INFORMATION................................................................................................................ 432
P
ACKAGE
D
IMENSIONS
.............................................................................................................................. 432
R
EVISIONS
................................................................................................................................................ 433