
XRT84L38
388
OCTAL T1/E1/J1 FRAMER
REV. 1.0.1
The table below shows configurations of the Alarm and Error Interrupt Enable bit of the Block Interrupt Enable
Register.
BLOCK INTERRUPT ENABLE REGISTER (BIER) (INDIRECT ADDRESS = 0XNAH, 0X01H)
When these interrupt enable bits are set and CAS Multi-frame Yellow Alarm is present in the incoming E1
frame, the XRT84L38 framer will declare CAS Multi-frame Yellow Alarm by doing the following:
Set the Receive CAS Multi-frame Yellow Alarm State Change bit of the Alarm and Error Status Register to
one indicating there is a change in state of CAS Multi-frame Yellow Alarm. This status indicator is valid until
the Framer Interrupt Status Register is read.
Reading this register clears the associated interrupt if Reset-Upon-Read is selected in Interrupt Control
Register (ICR). Otherwise, a write-to-clear operation by the microprocessor is required to reset these status
indicators.
The table below shows the Receive CAS Multi-frame Yellow Alarm State Change status bits of the Alarm and
Error Status Register.
ALARM AND ERROR STATUS REGISTER (AESR) (INDIRECT ADDRESS = 0XNAH, 0X02H)
12.5.5
How to configure the framer to detect Bipolar Violation
The line coding for the E1 signal should be bipolar. That is, a binary "0" is received as zero volts while a binary
"1" is received as either a positive or negative pulse, opposite in polarity to the previous pulse. A Bipolar
Violation or BPV occurs when the alternate polarity rule is violated. The Alarm indication logic within the
Receive Framer block of the XRT84L38 framer monitors the incoming E1 frames for Bipolar Violations.
If a Bipolar Violation is present in the incoming E1 frame, the XRT84L38 framer can generate a Receive
Bipolar Violation interrupt associated with the setting of Receive Bipolar Violation bit of the Alarm and Error
Status Register to one.
To enable the Receive Bipolar Violation interrupt, the Receive Bipolar Violation Interrupt Enable bit of the Alarm
and Error Interrupt Enable Register (AEIER) has to be set to one. In addition, the Alarm and Error Interrupt
Enable bit of the Block Interrupt Enable Register (BIER) needs to be one.
B
IT
N
UMBER
B
IT
N
AME
B
IT
T
YPE
B
IT
D
ESCRIPTION
1
Alarm and Error
Interrupt Enable
R/W
0 - Every interrupt generated by the Alarm and Error Interrupt Status Reg-
ister (AEISR) is disabled.
1 - Every interrupt generated by the Alarm and Error Interrupt Status Reg-
ister (AEISR) is enabled.
B
IT
N
UMBER
B
IT
N
AME
B
IT
T
YPE
B
IT
D
ESCRIPTION
5
Receive CAS
Multi-frame Yellow
Alarm State
Change
RUR /
WC
0 - There is no change of CAS Multi-frame Yellow Alarm state in the incom-
ing E1 payload data.
1 - There is change of CAS Multi-frame Yellow Alarm state in the incoming
E1 payload data.