
XRT84L38
392
OCTAL T1/E1/J1 FRAMER
REV. 1.0.1
The SLC96 Enable bit and the LAPD Enable bit of the Data Link Control Register (DLCR) determines which
one of the three functions is performed by the Transmit HDLC Controller block. The table below shows
configuration of the SLC96 Enable bit of the Data Link Control Register (DLCR).
DATA LINK CONTROL REGISTER (DLCR) INDIRECT ADDRESS = 0XN0H, 0X13H)
The table below shows configuration of the LAPD Enable bit of the Data Link Control Register (DLCR).
DATA LINK CONTROL REGISTER (DLCR) (INDIRECT ADDRESS = 0XN0H, 0X13H)
13.1.2
How to configure XRT84L38 to transmit data link information through D or E Channels
The XRT84L38 can configure any one or ones of the twenty-four DS0 channels to be D or E channels. D
channel is used primarily for data link applications. E channel is used primarily for signaling for circuit switching
with multiple access configurations.
The Transmit Data Conditioning Select [3:0] bits of the Transmit Channel Control Register (TCCR) of each
channel determine whether that particular channel is configured as D or E channel. These bits also determine
what type of data or signaling conditioning is applied to each channel.
TRANSMIT CHANNEL CONTROL REGISTER (TCCR) (INDIRECT ADDRESS = 0XN2H, 0X00H - 0X1FH)
If the Transmit Data Conditioning Select [3:0] bits of the Transmit Channel Control Register of a particular
timeslot are set to 1111, that timeslot is configured as a D or E timeslot.
Any D or E timeslot can be configured to take data link information from the following sources:
DS1 Transmit Overhead Output Interface Block
DS1 Transmit HDLC Controller Block
DS1 Transmit Serial Output Interface Block
DS1 Transmit Fractional Input Interface Block
The Transmit D or E Channel Source Select [1:0] bits of the Transmit Data Link Select Register (TSDLSR)
determines which one of the above-mentioned modules to be input sources of D or E timeslot. The table below
B
IT
N
UMBER
B
IT
N
AME
B
IT
T
YPE
B
IT
D
ESCRIPTION
7
SLC96 Enable
R/W
0 - In SLC96 framing mode, the data link transmission is disabled. The framer
transmits the regular SF framing bits.
In ESF framing mode, the framer transmits regular ESF framing bits and Facility
Data Link (FDL) bits.
1 - In SLC96 framing mode, the data link transmission is enabled.
In ESF framing mode, the framer transmits SLC96-like message in the Facility
Data Link bits.
B
IT
N
UMBER
B
IT
N
AME
B
IT
T
YPE
B
IT
D
ESCRIPTION
0
LAPD Enable
R/W
0 - The Transmit HDLC Controller will send out Bit-Oriented Signaling (BOS)
message.
1 - The Transmit HDLC Controller will send out LAPD protocol or so-called Mes-
sage-Oriented Signaling (MOS) message.
B
IT
N
UMBER
B
IT
N
AME
B
IT
T
YPE
B
IT
D
ESCRIPTION
3-0
Transmit Data
Conditioning
Select
R/W
1111 - This channel is configured as D or E timeslot.