TABLE 24:
參數(shù)資料
型號： XRT72L71IQ
廠商： Exar Corporation
文件頁數(shù)： 64/102頁
文件大小： 0K
描述： IC FRAMER DS3 ATM UNI 160PQFP
產(chǎn)品變化通告： XRT72Lx Series Obsolescence 02/May/2012
標(biāo)準(zhǔn)包裝： 24
控制器類型： DS3 ATM UNI，透明通道調(diào)幀器
電源電壓： 3.3V
電流 - 電源： 120mA
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 160-BQFP
供應(yīng)商設(shè)備封裝： 160-PQFP（28x28）
包裝： 托盤
XRT72L71
á
DS3 ATM UNI/CLEAR CHANNEL FRAMER
REV. 1.1.0
60
TABLE 24: TX DS3 M-BIT MASK REGISTER
REGISTER 23
TX DS3 M-BIT MASK REGISTER
HEX ADDRESS: 0X17
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
7
Tx FEBE Dat(2)
R/W
0
The Transmit DS3 Framer block will transmit the value “TxFEBEDat[2:0]”
within the “FEBE” bit-fields, if the “FEBE Register Enable” bit-field is set to
“1”.
NOTE: This bit-field is only active if the XRT72L71 is configured to support
the “C-bit Parity” Framing Format.
6
Tx FEBE Dat(1)
R/W
0
5
Tx FEBE Dat(0)
R/W
0
4
FEBE Register Enable
R/W
0
0: FEBE bits, for transmission, are internally generated based on conditions,
as detected by the Receive DS3 Framer block.
1: Transmit FEBE bits are taken from the TxFEBEDat [2:0] register bits
NOTE: This bit-field is only active if the XRT72L71 is configured to support
the “C-bit Parity” Framing Format.
3
Mbit Mask(2)
R/W
0
The Transmit DS3 Framer block performs an XOR operation of the MBitMask
bits with the corresponding “M” bit, within each outbound DS3 frame.
MBitMask(2) corresponds to first M-Bit (M0) in DS3 frame,
MBitMask(1) corresponds to second M-Bit (M1) in DS3 frame,
MBitMask(0) corresponds to last M-Bit (M0) in DS3 frame
NOTES:
1. Setting any of these bit-fields to “1”, will cause an “erred” M-bit to be
transmitted onto the line.
2. For normal operation, the user should set each of these bit-fields to
“0”.
2
Mbit Mask(1)
R/W
0
1
Mbit Mask(0)
R/W
0
TxError PBit
R/W
0
0: P Bits are calculated from input payload and inserted into the P-bit fields.
1: Calculated P Bits are inverted before transmission (thereby creating a “P-
Bit” Error).
NOTE: For normal operation, set this bit-field to “0”.
TABLE 25: TX DS3 F-BIT MASK1 REGISTER
REGISTER 24
TX DS3 F-BIT MASK1 REGISTER
HEX ADDRESS: 0X18
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
7-4
Unused
RO
0
3
F-bit Mask (27)
R/W
0
The Transmit DS3 Framer block performs an XOR operation of the F-Bit
Mask bits, with the corresponding “F” bits, within each outbound DS3 frame.
FBitMask(0) corresponds to first F-Bit (F1) is the DS3 frame, FBitMask (1)
corresponds to 2nd F-Bit (F0)in the DS3 frame,...FBitMask(27) corresponds
to the last F-Bit of the M-Frame.
NOTES:
1. Setting any of these bit-fields to “1” will cause an “erred” F-bit to be
transmitted onto the line.
2. For normal operation, the user should set each of these bit-fields to
“0”.
2
F-bit Mask (26)
R/W
0
1
F-bit Mask (25)
R/W
0
F-bit Mask (24)
R/W
0
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