TABLE 16:
參數(shù)資料
型號: XRT72L71IQ
廠商: Exar Corporation
文件頁數(shù): 57/102頁
文件大?。?/td> 0K
描述: IC FRAMER DS3 ATM UNI 160PQFP
產(chǎn)品變化通告: XRT72Lx Series Obsolescence 02/May/2012
標(biāo)準(zhǔn)包裝: 24
控制器類型: DS3 ATM UNI,透明通道調(diào)幀器
電源電壓: 3.3V
電流 - 電源: 120mA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 160-BQFP
供應(yīng)商設(shè)備封裝: 160-PQFP(28x28)
包裝: 托盤
XRT72L71
á
DS3 ATM UNI/CLEAR CHANNEL FRAMER
REV. 1.1.0
54
TABLE 16: RXDS3 STATUS REGISTER
REGISTER 15
RXDS3 STATUS REGISTER
HEX ADDRESS:0X0F
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
7-5
Unused
RO
0
4
Rx FERF
RO
0
Receive FERF (Far-End Receive Failure) Alarm:
0: The Receive DS3 Framer block is NOT currently declaring the “FERF”
condition.
1: The Receive DS3 Framer block is currently declaring the “FERF” condi-
tion.
3Rx AIC
RO
0
Receive AIC (Application Identification Channe) State:
0: Indicates that the AIC bit-field was set to “0” within two or more of the last
15 M-frames. This indicates that the inbound DS3 data stream is of the “M13
Framing” format.
1: Incoming frame is found to be in the C-bit format (AIC bit = 1) for at least
63 consecutive M-frames. This indicates that the inbound DS3 data stream
is of the “C-bit Parity” Framing format.
2
Rx FEBE(2)
RO
0
Received FEBE (Far-End-Block Error) Value:
RxFEBE[2:0] contains the value of the most recently received FEBE value.
When RxFEBE[2:0] = 011, this indicates that the Remote Terminal has
detected CP-bits or Framing Bit Errors in its DS3 data stream.
When RxFEBE[2:0] = 111, this indicates that the Remote Terminal is not cur-
rently detecting any Framing Bit or CP-bit errors in its DS3 data stream.
NOTE: These bit-fields are only active if the XRT72L71 is configured to sup-
port the “C-bit Parity” Framing format.
1
RxFEBE(1)
RO
0
RxFEBE(0)
RO
0
TABLE 17: RX DS3 INTERRUPT ENABLE REGISTER
REGISTER 16
RX DS3 INTERRUPT ENABLE REGISTER
HEX ADDRESS: 0X10
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
7
CP Bit Error Interupt
Enable
R/W
0
0: Detection of CP-Bit Error Interrupt is disabled
1: Generates Interrupt upon Detection of CP (Path Parity) bit Error.
6
LOS Interrupt Enable
R/W
0
0: Change in LOS Condition Interrupt is disabled
1: Generates interrupt upon change of LOS (Loss of Signal) status
5
AIS Interrupt Enable
R/W
0
0: Change in AIS Condition Interrupt is disabled
1: Generates interrupt upon change of AIS (Alarm Indication Signal) status.
4
Idle Interrupt Enable
R/W
0
0: Change in Idle Condition Interrupt is disabled
1: Generates interrupt upon change of IDLE status
3
FERF Interrupt Enable
R/W
0
0: Change in FERF (Far-End Receive Failure) Condition Interrupt is disabled
1: Generates interrupt upon change in FERF Condition.
2
AIC Interrupt Enable
R/W
0
0: Change in AIC State Interrupt is disabled
1: Generates interrupt upon change of AIC values, in “inbound” DS3 data
steam.
1
OOF Interrupt Enable
R/W
0
0: Change in OOF (Out of Frame) Condition Interrupt is disabled
1: Generates interrupt upon change of OOF condition.
0
P-Bit Error Interrupt Enable
R/W
0
0: Detection of P-Bit Error Interrupt disabled
1: Generates interrupt upon Detection of P-bit Error.
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