參數(shù)資料
型號: XRT72L71IQ
廠商: Exar Corporation
文件頁數(shù): 16/102頁
文件大小: 0K
描述: IC FRAMER DS3 ATM UNI 160PQFP
產(chǎn)品變化通告: XRT72Lx Series Obsolescence 02/May/2012
標(biāo)準(zhǔn)包裝: 24
控制器類型: DS3 ATM UNI,透明通道調(diào)幀器
電源電壓: 3.3V
電流 - 電源: 120mA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 160-BQFP
供應(yīng)商設(shè)備封裝: 160-PQFP(28x28)
包裝: 托盤
XRT72L71
á
DS3 ATM UNI/CLEAR CHANNEL FRAMER
REV. 1.1.0
16
102
StuffCtl
I
External PLCP Frame Stuff Control: This input allows the user to externally
exercise or forego trailer nibble stuffing opportunities by the Transmit PLCP
Processor. PLCP trailer nibble stuff opportunities occur in periods of three
PLCP frames (375s). The first PLCP frame (first within a “stuff opportunity”
period) will have 13 trailer nibbles appended to it. The second PLCP frame
(second within a “stuff opportunity” period) will have 14 trailer nibbles
appended to it. The third PLCP frame (the location of the stuff opportunity) will
contain 13 trailer nibbles if the StuffCtl input is “Low” and 14 trailer nibbles is
the StuffCtl input is “High”.
NOTE: The user should tie this input pin to “GND” whenever the XRT72L71
has been configured to operate in the “Clear-Channel-Framer” Mode.
103
TxInClk
I
Transmit DS3 Framer Block—Clock Signal: The Transmit DS3 Framer can
be configured to use this input signal as the timing reference. If this input pin is
chosen to be the timing reference, then the user must supply a "High" quality
44.736 MHz signal to this input pin. In this configuration, frame generation, by
the Transmit DS3 Framer, will be asynchronous (with any other timing signals
within the UNI). However, frame timing will be based upon this clock signal.
NOTE: This input pin should be tied to “GND” if it is not used as the Transmit
DS3 Framer timing reference.
104
RxPLOF
O
Receive PLCP—“Loss of Frame” Output Indicator: The Receive PLCP
Processor will assert this pin, when it declares a “Loss of Frame” condition. This
output will be negated when the Receive PLCP Processor reaches the “In
Frame” Condition.
NOTE: This output pin is only active if the user has configured the XRT72L71
to operate in the “ATM UNI” Mode.
105
GND
***
Ground Signal Pin
106
RxPOOF
O
Receive PLCP “Out of Frame” Indicator: The Receive PLCP Processor will
assert this pin, when it declares an “Out of Frame” condition. This output will
be negated when the Receive PLCP Processor reaches the “In Frame” Condi-
tion.
NOTE: This output pin is only active if the user has configured the XRT72L71
to operate in the “ATM UNI” Mode.
107
TxFrameRef
I
Transmit DS3 Framer—Frame Reference Input Pin: The Transmit DS3
Framer can be configured to use this input signal as the “framing” reference for
the Transmit DS3 Framer block. If this input pin is chosen to be the timing ref-
erence, then any rising edge at this input will cause the Transmit DS3 Framer
to begin its creation a new DS3 M-frame. Consequently, the user must supply
a clock signal that is equivalent to the DS3 Frame rate (or 9398.3 Hz). Fur-
ther, the signal which is driving this input pin, must be synchronized witht he
44.736MHz clock signal, which is applied to the “TxInClk” input pin.
NOTE: This input pin should be tied to “GND” if it is not used as the Transmit
DS3 Framer frame reference signal.
PIN DESCRIPTION (CONTINUED)
PIN NO.
SYMBOL
TYPE
DESCRIPTION
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