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參數(shù)資料
| 型號： | XRT72L71IQ |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 44/102頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FRAMER DS3 ATM UNI 160PQFP |
| 產(chǎn)品變化通告： | XRT72Lx Series Obsolescence 02/May/2012 |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 控制器類型： | DS3 ATM UNI，透明通道調(diào)幀器 |
| 電源電壓： | 3.3V |
| 電流 - 電源： | 120mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 160-BQFP |
| 供應(yīng)商設(shè)備封裝： | 160-PQFP（28x28） |
| 包裝： | 托盤 |
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XRT72L71
á
DS3 ATM UNI/CLEAR CHANNEL FRAMER
REV. 1.1.0
42
TRANSMIT CELL PROCESSOR BLOCK
Optionally computes and inserts HEC byte into all
cells (user, OAM and Idle).
Optionally scrambles the payload of each cell.
Idle cells are automatically generated when no user
cells are available in the TxFIFO.
UNI contains on-chip registers that support the
generation/transmission of default or custom Idle
cells.
UNI contains the on-chip “Transmit OAM Cell” buffer
(54 bytes) that allows the user to write in and store
the contents of OAM cells, in preparation for trans-
mission.
OAM cells are transmitted upon software command.
Performs “Data Path Integrity” check on all incoming
cell data, originating from the ATM Layer processor.
Provides a serial input port to allow the user to
insert the GFC (Generic Flow Control) field exter-
nally into the GFC nibble field of an outbound (e.g.,
Transmit direction) valid ATM Cell.
RECEIVE CELL PROCESSOR BLOCK
Performs cell delineation on either “Direct Mapped”
ATM cell data or PLCP frames.
Verifies the HEC bytes of incoming cells and cor-
rects most cells with single bit errors. Cells with
multi-bit errors are detected and are optionally dis-
carded.
(Optionally) Performs filtering of Idle Cells.
(Optionally) Performs filtering of User and OAM cells.
UNI contains on-chip buffer space (“Receive OAM
Cell” buffer) that allows for the reception and pro-
cessing of selected OAM cells.
Optionally de-scrambles the payload of each cell.
Provides a serial output port that allows the user to
read the GFC value of an incoming (e.g., Receive
direction) ATM Cell.
Inserts the “Data Path Integrity Check” patterns in
all cells that are written to the RxFIFO.
TRANSMIT PLCP PROCESSOR BLOCK
Can be disabled to support the “Direct Mapped”
ATM mode.
Packs 12 ATM cells into each PLCP frame along
with various other overhead bytes.
The Transmit PLCP Processor will automatically
determine its own stuffing options.
Overhead bytes include those that support BIP-8
calculations (B1), indicator of stuff-option status for
current PLCP frame (C1), diagnostic byte that
reflects alarms conditions that were detected in the
Receive Section of the UNI (G1); and Path Over-
head bytes.
Provides a serial input port for user to insert PLCP
Overhead Bytes externally.
RECEIVE PLCP PROCESSOR BLOCK
Can be disabled to support the “Direct Mapped”
ATM mode.
Determines the frame boundaries of incoming
PLCP frames (from the Receive DS3 Framer).
Extracts and processes the PLCP frame overhead
bytes.
Provides a serial output port for user to read in the
contents of the PLCP Overhead Bytes from the
incoming data.
TRANSMIT/RECEIVE DS3 FRAMER BLOCK
Supports the M13 and C-bit Parity Framing Formats.
Transmit and Receive DS3 Framers can transmit/
receive data in the Unipolar or the Bipolar (AMI or
B3ZS line codes) format.
The Transmit DS3 Framer provides a serial input
port that allows the user to insert his/her own
values for the overhead bits of the “outbound”
DS3 frames.
The Receive DS3 Framer provides a serial output
port that allows the user access to the values of the
overhead bits of the “incoming” DS3 frames.
The Receive DS3 Framer can be configured to
sample the incoming DS3 data (at the RxPOS and
RxNEG input pins) via the rising edge or falling
edge of the Receive Line Clock (RxLineClk) input.
The Transmit DS3 Framer can be configured to
update the “outbound” DS3 data (at the TxPOS and
TxNEG output pins) at the rising edge or falling
edge of the Transmit Line Clock (TxLineClk) output.
UNI includes on-chip RAM space to support the trans-
mission and reception of path maintenance data link
messages via an on-chip LAPD Transceiver
UNI includes on-chip registers to support the trans-
mission and reception of FEAC (Far End Alarm &
Control) messages via an on-chip FEAC Transceiver.
Contains on-chip FEAC Transceiver.
Contains on-chip LAPD Transceiver.
MICROPROCESSOR INTERFACE SECTION
Can be interfaced to Motorola or Intel type of micro-
processors/microcontrollers
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT72L71IQ-F | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Single CH DS3 UNI (3.3V) RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| XRT72L73IB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
| XRT72L74IB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
| XRT7300 | 制造商:EXAR 制造商全稱:EXAR 功能描述:E3/DS3/STS-1 LINE INTERFACE UNIT |
| XRT7300ES | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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