
XRT72L71
á
DS3 ATM UNI/CLEAR CHANNEL FRAMER
REV. 1.1.0
2
FIGURE 2. BLOCK DIAGRAM OF THE XRT72L71 DS3 UNI
Test and Diagnostic
Line Interface
Drive and Scan
Performance
Monitor
Receive
DS3
Framer
Receive Cell
Processor
Receive
UTOPIA
Interface
Transmitter
Receiver
LAPD
Transceiver
Microprocessor
Interface
(Programmable
Registers and
Interrupt Block)
FEAC
Processor
Transmit
UTOPIA
Interface
TxUClk
TxUData[15:0]
TxUPrty
TxUSoC
TxUEn
TxUClav
TxUAddr[4:0]
Transmit PLCP
Processor/
Clear Channel
Transmit Serial Data
Processor
Transmit
DS3
Framer
Receive PLCP
Processor/
Clear Channel
Receive Serial Data
Processor
16
cell
FIFO
16
cell
FIFO
2x54b OAM
Buffer
Transmit Cell
Processor
54b OAM Buffer
A[8:0]
WR_RW
RD_DS
CS
ALE_AS
Reset
Int
D[15:0]
Width16
MOTO/Intel
RDY_DTCK
TxPOS
TxNEG
TxFrame
TxOHClk
TxLineClk
TxAISEn
TxFrameRef
TxInClk
TxOHIns
TxOHFrame
TxOH
TxPOHFrame
8KRef
StuffCtl
TxOHInd/TxPFrame
TxSerData/TxPOH
TxPOHClk
TxPOHIns
TxCellTxed
TxGFCClk
TxGFCMSB
TxGFC
TDO
TDI
TestMode
TCK
TMS
TAOS
DMO
RLOL
TxLev
RLOOP
LLOOP
Req
RxRed
EncoDis
RxLineClk
RxNEG
RxPOS
RLOS
RxAIS
RxOHClk
RxOH
RxSerClk
RxLOS
RxFrame
RxOHFrame
RxOOF
RxPRed
RxPOHFrame
RxSerClk/RxPOHClk
RxSerData/RxPOH
RxOHInd/RxPFrame
RxPLOF
RxPOOF
RxLCD
RxCellRxed
RxGFCClk
RxGFCMSB
RxGFC
RxUClk
RxUEn
RxUPrty
RxUData[15:0]
RxUSoC
RxUClav
RxUAddr[4:0]