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參數(shù)資料
| 型號： | W942504CH-7 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | DRAM |
| 英文描述： | 64M X 4 DDR DRAM, 0.75 ns, PDSO66 |
| 封裝： | 0.400 X 0.875 INCH, 0.65 MM PITCH, TSOP2-66 |
| 文件頁數(shù)： | 8/45頁 |
| 文件大?。?/td> | 1261K |
| 代理商： | W942504CH-7 |
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W942504CH
- 16 -
Function Truth Table, continued
CURRENT
STATE
CS RAS
CAS
WE
ADDRESS
COMMAND
ACTION
NOTES
H
X
DSL
Nop->ROW active after tWR
L
H
X
NOP
Nop->ROW active after tWR
L
H
L
X
BST
ILLEGAL
L
H
L
H
BS, CA, A10
READ/READA
ILLEGAL
3
L
H
L
BS, CA, A10
WRIT/WRITA
ILLEGAL
3
L
H
BS, RA
ACT
ILLEGAL
3
L
H
L
BS,A10
PRE/PREA
ILLEGAL
3
L
H
X
AREF/SELF
ILLEGAL
Write
Recovering
L
Op-Code
MRS/EMRS
ILLEGAL
H
X
DSL
Nop->Enter precharge after tWR
L
H
X
NOP
Nop->Enter precharge after tWR
L
H
L
X
BST
ILLEGAL
L
H
L
H
BS, CA, A10
READ/READA
ILLEGAL
3
L
H
L
BS, CA, A10
WRIT/WRITA
ILLEGAL
3
L
H
BS, RA
ACT
ILLEGAL
3
L
H
L
BS, A10
PRE/PREA
ILLEGAL
3
L
H
X
AREF/SELF
ILLEGAL
Write
Recovering
with Auto
Precharge
L
Op-Code
MRS/EMRS
ILLEGAL
H
X
DSL
Nop->Idle after tRC
L
H
X
NOP
Nop->Idle after tRC
L
H
L
X
BST
ILLEGAL
L
H
L
H
X
READ/WRIT
ILLEGAL
L
H
X
ACT/PRE/PREA
ILLEGAL
Refreshing
L
X
AREF/SELF/MRS/
EMRS
ILLEGAL
H
X
DSL
Nop->Row after tMRD
L
H
X
NOP
Nop->Row after tMRD
L
H
L
X
BST
ILLEGAL
L
H
L
X
READ/WRIT
ILLEGAL
Mode
Register
Accessing
L
X
ACT/PRE/PREA/ARE
F/SELF/MRS/EMRS
ILLEGAL
Notes
:
1. All entries assume that CKE was active (High level) during the preceding clock cycle and the current clock cycle.
2. Illegal if any bank is not idle.
3. Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BS), depending on the state
of that bank.
4. Illegal if tRCD is not satisfied.
5. Illegal if tRAS is not satisfied.
6. Must satisfy burst interrupt condition.
7. Must avoid bus contention, bus turn around, and/or satisfy write recovery requirements.
8. Must mask preceding data which don’t satisfy tWR
Remark: H = High level, L = Low level, X = High or Low level (Don’t care), V = Valid data
相關PDF資料 |
PDF描述 |
|---|---|
| W9864G6IH-6 | 4M X 16 DDR DRAM, 5 ns, PDSO54 |
| WA-1RX33-A4 | SNAP ACTING/LIMIT SWITCH |
| WA-A325CBM | Peripheral Interface |
| WA-A325CPC | Peripheral Interface |
| WA-A325CPI | Peripheral Interface |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| W942508BH | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DRAM |
| W942508CH | 制造商:WINBOND 制造商全稱:Winbond 功能描述:8M x 4 BANKS x 8 BIT DDR SDRAM |
| W942508CH-5 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:8M x 4 BANKS x 8 BIT DDR SDRAM |
| W942508CH-6 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:8M x 4 BANKS x 8 BIT DDR SDRAM |
| W942508CH-7 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:8M x 4 BANKS x 8 BIT DDR SDRAM |
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