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參數(shù)資料
| 型號： | W942504CH-7 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | DRAM |
| 英文描述： | 64M X 4 DDR DRAM, 0.75 ns, PDSO66 |
| 封裝： | 0.400 X 0.875 INCH, 0.65 MM PITCH, TSOP2-66 |
| 文件頁數(shù)： | 13/45頁 |
| 文件大?。?/td> | 1261K |
| 代理商： | W942504CH-7 |
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W942504CH
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5. Write with Auto Precharge Command
( RAS = "H", CAS = "L", WE = "L", BS0, BS1 = Bank, A10 = "H", A0 to A9, A11 = Column
Address)
The Write with Auto Precharge command performs the Precharge operation automatically after the
Write operation. This command must not be interrupted by any other commands.
6. Read Command
( RAS = "H", CAS = "L", WE = "H", BS0, BS1 = Bank, A10 = "L", A0 to A9, A11 = Column
Address)
The Read command performs a Read operation to the bank designated by BS. The read data are
synchronized with both edges of DQS. The length of read data (Burst Length), Addressing Mode
and CAS Latency (access time from CAS command in a clock cycle) must be programmed in
the Mode Register at power-up prior to the Read operation.
7. Read with Auto Precharge Command
( RAS = "H", CAS = "L", WE = "H", BS0, BS1 = Bank, A10 = "H", A0 to A9, A11 = Column
Address)
The Read with Auto precharge command automatically performs the Precharge operation after the
Read operation.
1) READA
≥ tRAS (min) - (BL/2) x tCK
Internal precharge operation begins after BL/2 cycle from Read with Auto Precharge command.
2) tRCD(min)
≤ READA < tRAS(min) - (BL/2) x tCK
Data can be read with shortest latency, but the internal Precharge operation does not begin until
after tRAS (min) has completed.
This command must not be interrupted by any other command.
8. Mode Register Set Command
( RAS = "L", CAS = "L", WE = "L", BS0 = "L", BS1 = "L", A0 to A12 = Register Data)
The Mode Register Set command programs the values of CAS latency, Addressing Mode, Burst
Length and DLL reset in the Mode Register. The default values in the Mode Register after power-
up are undefined, therefore this command must be issued during the power-up sequence. Also,
this command can be issued while all banks are in the idle state. Refer to the table for specific
codes.
9. Extended Mode Register Set Command
( RAS = "L", CAS = "L", WE = "L", BS0 = "H", BS1 = "L", A0 to A12 = Register data)
The Extended Mode Register Set command can be implemented as needed for function
extensions to the standard (SDR-SDRAM). Currently the only available mode in EMRS is DLL
enable/disable, decoded by A0. The default value of the extended mode register is not defined;
therefore this command must be issued during the power-up sequence for enabling DLL. Refer to
the table for specific codes.
相關PDF資料 |
PDF描述 |
|---|---|
| W9864G6IH-6 | 4M X 16 DDR DRAM, 5 ns, PDSO54 |
| WA-1RX33-A4 | SNAP ACTING/LIMIT SWITCH |
| WA-A325CBM | Peripheral Interface |
| WA-A325CPC | Peripheral Interface |
| WA-A325CPI | Peripheral Interface |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| W942508BH | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DRAM |
| W942508CH | 制造商:WINBOND 制造商全稱:Winbond 功能描述:8M x 4 BANKS x 8 BIT DDR SDRAM |
| W942508CH-5 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:8M x 4 BANKS x 8 BIT DDR SDRAM |
| W942508CH-6 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:8M x 4 BANKS x 8 BIT DDR SDRAM |
| W942508CH-7 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:8M x 4 BANKS x 8 BIT DDR SDRAM |
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