參數(shù)資料
型號: W942504CH-7
廠商: WINBOND ELECTRONICS CORP
元件分類: DRAM
英文描述: 64M X 4 DDR DRAM, 0.75 ns, PDSO66
封裝: 0.400 X 0.875 INCH, 0.65 MM PITCH, TSOP2-66
文件頁數(shù): 18/45頁
文件大?。?/td> 1261K
代理商: W942504CH-7
W942504CH
Publication Release Date: February 14, 2003
- 25 -
Revision A1
Addressing sequence of Interleave mode
A Column access is started from the inputted column address and is performed by
interleaving the address bits in the sequence shown as the following.
Address Sequence for Interleave Mode
DATA
ACCESS ADDRESS
BURST LENGTH
Data 0
A8 A7 A6 A5 A4 A3 A2 A1 A0
2 words
Data 1
A8 A7 A6 A5 A4 A3 A2 A1 A0
Data 2
A8 A7 A6 A5 A4 A3 A2 A1 A0
4 words
Data 3
A8 A7 A6 A5 A4 A3 A2 A1 A0
Data 4
A8 A7 A6 A5 A4 A3 A2 A1 A0
8 words
Data 5
A8 A7 A6 A5 A4 A3 A2 A1 A0
Data 6
A8 A7 A6 A5 A4 A3 A2 A1 A0
Data 7
A8 A7 A6 A5 A4 A3 A2 A1 A0
3.
CAS Latency field (A6 to A4)
This field specifies the number of clock cycles from the assertion of the Read command to the first
data read. The minimum values of CAS Latency depends on the frequency of CLK.
A6
A5
A4
CAS
Latency
0
Reserved
0
1
Reserved
0
1
0
2
0
1
Reserved
1
0
Reserved
1
0
1
Reserved
1
0
2.5
1
Reserved
4. DLL Reset bit (A8)
This bit is used to reset DLL. When the A8 bit is "1", DLL is reset.
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