參數(shù)資料
型號(hào)： W942504CH-7
廠商： WINBOND ELECTRONICS CORP
元件分類： DRAM
英文描述： 64M X 4 DDR DRAM, 0.75 ns, PDSO66
封裝： 0.400 X 0.875 INCH, 0.65 MM PITCH, TSOP2-66
文件頁(yè)數(shù)： 16/45頁(yè)
文件大小： 1261K
代理商： W942504CH-7
W942504CH
Publication Release Date: February 14, 2003
- 23 -
Revision A1
When the Burst Read Stop command is issued for the bank in a Burst Read cycle, the Burst Read
operation is terminated. The Burst read Stop command is not supported during a write burst operation.
Refer to the diagrams for Burst termination.
Refresh Operation
Two types of Refresh operation can be performed on the device: Auto Refresh and Self Refresh. By
repeating the Auto Refresh cycle, each bank in turn refreshed automatically. The Refresh operation
must be performed 8192 times (rows) within 64 mS. The period between the Auto Refresh command
and the next command is specified by tRFC.
Self Refresh mode enter issuing the Self Refresh command (CKE asserted "low"). while all banks are
in the idle state. The device is in Self Refresh mode for as long as cke held "low". In the case of 8192
burst Auto Refresh commands, 8192 burst Auto Refresh commands must be performed within 7.8us
before entering and after exiting the Self Refresh mode. In the case of distributed Auto Refresh
commands, distributed auto refresh commands must be issued every 7.8
S and the last distributed
Auto Refresh commands must be performed within 7.8us before entering the self refresh mode. After
exiting from the Self Refresh mode, the refresh operation must be performed within 7.8
S. In Self
Refresh mode, all input/output buffers are disable, resulting in lower power dissipation (except CKE
buffer). Refer to the diagrams for Refresh operation.
Power Down Mode
Two types of Power Down Mode can be performed on the device: Active Standby Power Down Mode
and Precharge Standby Power Down Mode.
When the device enters the Power Down Mode, all input/output buffers and DLL are disabled resulting
in low power dissipation (except CKE buffer).
Power Down Mode enter asserting CKE "low" while the device is not running a burst cycle. Taking
CKE: "high" can exit this mode. When CKE goes high, a No operation command must be input at next
CLK rising edge. Refer to the diagrams for Power Down Mode.
Mode Register Operation
The mode register is programmed by the Mode Register Set command (MRS/EMRS) when all banks
are in the idle state. The data to be set in the Mode Register is transferred using the A0 to A12 and
BS0, BS1 address inputs.
The Mode Register designates the operation mode for the read or write cycle. The register is divided
into five filed: (1) Burst Length field to set the length of burst data (2) Addressing Mode selected bit to
designate the column access sequence in a Burst cycle (3) CAS Latency field to set the assess time
in clock cycle (4) DLL reset field to reset the dll (5) Regular/Extended Mode Register filed to select a
type of MRS (Regular/Extended MRS). EMRS cycle can be implemented the extended function (DLL
enable/Disable mode)
The initial value of the Mode Register (including EMRS) after power up is undefined; therefore the
Mode Register Set command must be issued before power operation.
相關(guān)PDF資料
PDF描述
W9864G6IH-6 4M X 16 DDR DRAM, 5 ns, PDSO54
WA-1RX33-A4 SNAP ACTING/LIMIT SWITCH
WA-A325CBM Peripheral Interface
WA-A325CPC Peripheral Interface
WA-A325CPI Peripheral Interface
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
W942508BH 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DRAM
W942508CH 制造商:WINBOND 制造商全稱:Winbond 功能描述:8M x 4 BANKS x 8 BIT DDR SDRAM
W942508CH-5 制造商:WINBOND 制造商全稱:Winbond 功能描述:8M x 4 BANKS x 8 BIT DDR SDRAM
W942508CH-6 制造商:WINBOND 制造商全稱:Winbond 功能描述:8M x 4 BANKS x 8 BIT DDR SDRAM
W942508CH-7 制造商:WINBOND 制造商全稱:Winbond 功能描述:8M x 4 BANKS x 8 BIT DDR SDRAM
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