參數(shù)資料
型號(hào)： W942504CH-7
廠商： WINBOND ELECTRONICS CORP
元件分類： DRAM
英文描述： 64M X 4 DDR DRAM, 0.75 ns, PDSO66
封裝： 0.400 X 0.875 INCH, 0.65 MM PITCH, TSOP2-66
文件頁(yè)數(shù)： 23/45頁(yè)
文件大?。?/td> 1261K
代理商： W942504CH-7
W942504CH
Publication Release Date: February 14, 2003
- 3 -
Revision A1
1. GENERAL DESCRIPTION
W942504CH is a CMOS Double Data Rate synchronous dynamic random access memory (DDR
SDRAM), organized as 16,777,216 words
× 4 banks × 4 bits. Using pipelined architecture and 0.13 m
process technology, W942504CH delivers a data bandwidth of up to 286M words per second (-7). To
fully comply with the personal computer industrial standard, W942504CH is sorted into three speed
grades: -7, -75 and The -7 is compliant to the 143 MHz/CL2.5 or DDR266/CL2 specification, the -75 is
compliant to the DDR266/CL2.5 specification.
All Inputs reference to the positive edge of CLK (except for DQ, DM, and CKE). The timing reference
point for the differential clock is when the CLK and CLK signals cross during a transition. And Write
and Read data are synschronized with the both edges of DQS (Data Strobe).
By having a programmable Mode Register, the system can change burst length, latency cycle,
interleave or sequential burst to maximize its performance. W942504CH is ideal for main memory in
high performance applications.
2. FEATURES
2.5V
±0.2V Power Supply
Up to 143 MHz Clock Frequency
Double Data Rate architecture; two data transfers per clock cycle
Differential Clock Inputs (CLK and CLK )
DQS is edge-aligned with data for Read; center-aligned with data for Write
CAS Latency: 2 and 2.5
Burst Length: 2, 4 and 8
Auto Refresh and Self Refresh
Precharged Power Down and Active Power Down
Write Data Mask
Write Latency = 1
8K Refresh Cycles /64 mS
Interface: SSTL-2
Packaged in TSOP II 66-pin, 400 x 875 mil, 0.65 mm pin pitch
3. KEY PARAMETERS
SYMBOL
DESCRIPTION
MIN./MAX.
-7
-75
tCK
Clock Cycle Time
CL = 2
Min.
7.5 nS
8 nS
CL = 2.5
Min.
7 nS
7.5 nS
tRAS
Active to Precharge Command Period
Min.
45 nS
tRC
Active to Ref/Active Command Period
Min.
65 nS
IDD1
Operation Current (Single bank)
Max.
120 mA
IDD4
BURST OPERATION CURRENT
Max.
165 mA
155 mA
IDD6
Self-Refresh Current
Max.
3 mA
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
W942508BH 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DRAM
W942508CH 制造商:WINBOND 制造商全稱:Winbond 功能描述:8M x 4 BANKS x 8 BIT DDR SDRAM
W942508CH-5 制造商:WINBOND 制造商全稱:Winbond 功能描述:8M x 4 BANKS x 8 BIT DDR SDRAM
W942508CH-6 制造商:WINBOND 制造商全稱:Winbond 功能描述:8M x 4 BANKS x 8 BIT DDR SDRAM
W942508CH-7 制造商:WINBOND 制造商全稱:Winbond 功能描述:8M x 4 BANKS x 8 BIT DDR SDRAM
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