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參數(shù)資料
| 型號： | W942504CH-7 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | DRAM |
| 英文描述： | 64M X 4 DDR DRAM, 0.75 ns, PDSO66 |
| 封裝： | 0.400 X 0.875 INCH, 0.65 MM PITCH, TSOP2-66 |
| 文件頁數(shù)： | 14/45頁 |
| 文件大?。?/td> | 1261K |
| 代理商： | W942504CH-7 |
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W942504CH
Publication Release Date: February 14, 2003
- 21 -
Revision A1
10. No-Operation Command
( RAS = "H", CAS = "H", WE = "H")
The No-Operation command simply performs no operation (same command as Device Deselect).
11. Burst Read Stop Command
( RAS = "H", CAS = "H", WE = "L")
The Burst stop command is used to stop the burst operation. This command is only valid during a
Burst Read operation.
12. Device Deselect Command
( CS = "H")
The Device Deselect command disables the command decoder so that the RAS , CAS ,
WE
and Address inputs are ignored. This command is similar to the No-Operation command.
13. Auto Refresh Command
( RAS = "L", CAS = "L", WE = "H", CKE = "L", BS0, BS1, A0 to A12 = Don’t care)
The Auto Refresh command is used to refresh the row address provided by the internal refresh
counter. The Refresh operation must be performed 8192 times within 64 mS. The next command
can be issued after tREF from the end of the Auto Refresh command. When the Auto Refresh
command is used, all banks must be in the idle state.
14. Self Refresh Entry Command
( RAS = "L", CAS = "L", WE = "H", CKE = "L", BS0, BS1, A0 to A12 = Don’t care)
The Self Refresh Entry command is used to enter Self Refresh mode. While the device is in Self
Refresh mode, all input and output buffer (except the CKE buffer) are disabled and the Refresh
operation is automatically performed. Self Refresh mode is exited by taking CKE "high" (the Self
Refresh Exit command). During self refresh, DLLl is disable.
15. Self Refresh Exit Command
(CKE = "H", CS = "H" or CKE = "H", RAS = "H", CAS = "H")
This command is used to exit from Self Refresh mode. Any subsequent commands can be issued
after tXSNR (tXSRD for Read Command) from the end of this command.
16. Data Write Enable /Disable Command
(DM = "L/H" or LDM, UDM = "L/H")
During a Write cycle, the DM or LDM, UDM signal functions as Data Mask and can control every
word of the input data. The LDM signal controls DQ0 to DQ7 and UDM signal controls DQ8 to
DQ15.
相關PDF資料 |
PDF描述 |
|---|---|
| W9864G6IH-6 | 4M X 16 DDR DRAM, 5 ns, PDSO54 |
| WA-1RX33-A4 | SNAP ACTING/LIMIT SWITCH |
| WA-A325CBM | Peripheral Interface |
| WA-A325CPC | Peripheral Interface |
| WA-A325CPI | Peripheral Interface |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| W942508BH | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DRAM |
| W942508CH | 制造商:WINBOND 制造商全稱:Winbond 功能描述:8M x 4 BANKS x 8 BIT DDR SDRAM |
| W942508CH-5 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:8M x 4 BANKS x 8 BIT DDR SDRAM |
| W942508CH-6 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:8M x 4 BANKS x 8 BIT DDR SDRAM |
| W942508CH-7 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:8M x 4 BANKS x 8 BIT DDR SDRAM |
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