參數(shù)資料
型號(hào)： W942504CH-7
廠商： WINBOND ELECTRONICS CORP
元件分類： DRAM
英文描述： 64M X 4 DDR DRAM, 0.75 ns, PDSO66
封裝： 0.400 X 0.875 INCH, 0.65 MM PITCH, TSOP2-66
文件頁數(shù)： 45/45頁
文件大?。?/td> 1261K
代理商： W942504CH-7
W942504CH
Publication Release Date: February 14, 2003
- 9 -
Revision A1
DC Characteristics
SYM.
PARAMETER
-7
-75
UNIT
NOTES
IDD0
OPERATING CURRENT: One Bank Active-Precharge; tRC = tRC min; tCK
= tCK min; DQ, DM and DQS inputs changing twice per clock cycle;
Address and control inputs changing once per clock cycle
110
7
IDD1
OPERATING CURRENT: One Bank Active-Read-Precharge; Burst = 2;
tRC = tRC min; CL=2.5; tCK = tCK min; IOUT = 0 mA; Address and control
inputs changing once per clock cycle.
120
7, 9
IDD2P
PRECHARGE-POWER-DOWN STANDBY CURRENT: All Banks Idle;
Power down mode; CKE < VIL max; tCK = tCK min; Vin = VREF for DQ,
DQS and DM
2
IDD2F
IDLE FLOATING STANDBY CURRENT:
CS > VIH min; All Banks Idle;
CKE > VIH min; Address and other control inputs changing once per
clock cycle; Vin = Vref for DQ, DQS and DM
45
40
7
IDD2N
IDLE STANDBY CURRENT: CS > VIH min; All Banks Idle; CKE > VIH
min; tCK = tCK min; Address and other control inputs changing once per
clock cycle; Vin > VIH min or Vin < VIL max for DQ, DQS and DM
45
40
7
IDD2Q
IDLE QUIET STANDBY CURRENT: CS > VIH min; All Banks Idle; CKE
> VIH min; tCK = tCK min; Address and other control inputs stable; Vin >
VREF for DQ, DQS and DM
40
35
7
IDD3P
ACTIVE POWER-DOWN STANDBY CURRENT: One Bank Active;
Power down mode; CKE < VIL max; tCK = tCK min
20
IDD3N
ACTIVE STANDBY CURRENT: CS > VIH min; CKE > VIH min; One
Bank Active-Precharge; tRC = tRAS max; tCK = tCK min; DQ, DM and DQS
inputs changing twice per clock cycle; Address and other control inputs
changing once per clock cycle
70
65
7
IDD4R
OPERATING CURRENT: Burst=2; Reads; Continuous burst; One Bank
Active; Address and control inputs changing once per clock cycle;
CL=2.5; tCK = tCK min; IOUT=0mA
165
155
7, 9
IDD4W
OPERATING CURRENT: Burst=2; Write; Continuous burst; One Bank
Active; Address and control inputs changing once per clock cycle;
CL=2.5; tCK = tCK min; DQ, DM and DQS inputs changing twice per clock
cycle
165
155
7
IDD5
AUTO REFRESH CURRENT: tRC = tRFC min
190
7
IDD6
SELF REFRESH CURRENT: CKE < 0.2V
3
IDD7
RANDOM READ CURRENT: 4 Banks Active Read with activate every
20ns, Auto-Precharge Read every 20ns; Burst=4; tRCD= 3; IOUT= 0 mA;
DQ, DM and DQS inputs changing twice per clock cycle; Address
changing once per clock cycle
270
mA
CK
DQS
RANDOM READ CURRENT Timing
tRCD
tRC
tCK = 10ns
(
IDD7)
Bank 0
Row d
Bank 3
Row c
Bank 1
Row e
Bank 1
Row e
ADDRESS
Bank 0
Row d
Bank 2
Row f
Bank 3
Row q
Bank 2
Col f
READ
AP
ACT
READ
AP
COMMAND
READ
AP
ACT
READ
AP
ACT
DQ
Qa
Qb
Qc
Qd
Qe
Qa
Bank 0
Row h
ACT
Bank 0
Col d
READ
AP
ACT
Bank 1
Col e
Bank 2
Row f
Bank 3
Row q
Bank 2
Col f
Bank 0
Row h
READ
AP
Bank 1
Row e
Bank 3
Col c
Bank 0
Row d
相關(guān)PDF資料
PDF描述
W9864G6IH-6 4M X 16 DDR DRAM, 5 ns, PDSO54
WA-1RX33-A4 SNAP ACTING/LIMIT SWITCH
WA-A325CBM Peripheral Interface
WA-A325CPC Peripheral Interface
WA-A325CPI Peripheral Interface
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
W942508BH 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DRAM
W942508CH 制造商:WINBOND 制造商全稱:Winbond 功能描述:8M x 4 BANKS x 8 BIT DDR SDRAM
W942508CH-5 制造商:WINBOND 制造商全稱:Winbond 功能描述:8M x 4 BANKS x 8 BIT DDR SDRAM
W942508CH-6 制造商:WINBOND 制造商全稱:Winbond 功能描述:8M x 4 BANKS x 8 BIT DDR SDRAM
W942508CH-7 制造商:WINBOND 制造商全稱:Winbond 功能描述:8M x 4 BANKS x 8 BIT DDR SDRAM
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購

我的聯(lián)系方式

*
*
*