參數(shù)資料
型號: TSB41BA3AIGGM
廠商: Texas Instruments, Inc.
英文描述: IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER
中文描述: 的IEEE 1394b三端口電纜收發(fā)器/仲裁者
文件頁數(shù): 50/66頁
文件大?。?/td> 895K
代理商: TSB41BA3AIGGM
SLLS618B JUNE 2004 REVISED AUGUST 2004
50
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION (1394B INTERFACE)
The TSB41BA3A is designed to operate with a LLC such as the Texas Instruments TSB82AA2 when the
BMODE terminal is tied high. Details of operation for the Texas Instruments LLC devices are found in the
respective LLC data sheets. The following paragraphs describe the operation of the PHY-LLC interface. This
interface is formally specified in the IEEE 1394b-2002 standard.
The interface to the LLC consists of the PCLK, LCLK_PMC, CTL0CTL1, D0D7, LREQ, PINT, LPS, and
S5_LKON terminals on the TSB41BA3A, as shown in Figure 22.
S5_LKON
LPS
PCLK
LREQ
D0–D7
CTL0–CTL1
Link-Layer
Controller
TSB41BA3A
LCLK_PMC
PINT
Figure 22. PHY-LLC Interface
The LCLK_PMC terminal provides a clock signal to the PHY. The LLC derives this clock from the PCLK signal
and is phase-locked to the PCLK signal. All LLC to PHY transfers are synchronous to LCLK_PMC.
The PCLK terminal provides a 98.304-MHz interface system clock. All control, data, and PHY interrupt signals
are synchronized to the rising edge of PCLK.
The CTL0 and CTL1 terminals form a bidirectional control bus, which controls the flow of information and data
between the TSB41BA3A and LLC.
The D0D7 terminals form a bidirectional data bus, which transfers status information, control information, or
packet data between the devices. The TSB41BA3A supports S400B, S200B, and S100B data transfers over
the D0D7 data bus. In S400B, S200B, and S100B operation all Dn terminals are used.
The LREQ terminal is controlled by the LLC to send serial service requests to the PHY in order to request access
to the serial-bus for packet transmission, read or write PHY registers, or control arbitration acceleration. All data
on LREQ is synchronous to LCLK_PMC.
The LPS and S5_LKON terminals are used for power management of the PHY and LLC. The LPS terminal
indicates the power status of the LLC, and may be used to reset the PHY-LLC interface or to disable PCLK. The
S5_LKON terminal sends a wake-up notification to the LLC and indicates an interrupt to the LLC when either
LPS is inactive or the PHY register L bit is 0.
The PINT terminal is used by the PHY for the serial transfer of status, interrupt, and other information to the LLC.
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