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參數(shù)資料
| 型號： | TSB41BA3AIGGM |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER |
| 中文描述： | 的IEEE 1394b三端口電纜收發(fā)器/仲裁者 |
| 文件頁數(shù)： | 11/66頁 |
| 文件大?。?/td> | 895K |
| 代理商： | TSB41BA3AIGGM |
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SLLS618B JUNE 2004 REVISED AUGUST 2004
11
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions (Continued)
TERMINAL
NAME
TYPE
PFP
NO.
GGM
NO.
I/O
DESCRIPTION
PD
CMOS
77
H1
I
Power-down input. A high on this terminal turns off all internal circuitry. Asserting the PD
input high also activates an internal pulldown on the RESETz terminal to force a reset of the
internal control logic.
PINT
CMOS
1
J2
O
PHY Interrupt. The PHY uses this output to serially transfer status and interrupt information
to the link when PHY-link interface is in the 1394b mode. A bus holder is built into this
terminal.
PLLGND
Supply
25,
28
G9,
F9
PLL circuit ground terminals. These terminals must be tied together to the low-impedance
circuit board ground plane.
PLLVDD-CORE
Supply
29,
30
F8,
F7
PLL core circuit power terminals. A combination of high-frequency decoupling capacitors
near each terminal are suggested, such as paralleled 0.1
μ
F and 0.001
μ
F. An additional
1-
μ
F capacitor is required for voltage regulation. The PLLVDD-CORE terminals must be
separate from the DVDD-CORE terminals. These supply terminals are separated from the
DVDD-CORE, DVDD-3.3, PLLVDD-3.3 and AVDD-3.3 terminals internal to the device to
provide noise isolation.
PLLVDD-3.3
Supply
31
F6
PLL 3.3-V circuit power terminal. A combination of high-frequency decoupling capacitors
near the terminal are suggested, such as paralleled 0.1
μ
F and 0.001
μ
F. Lower frequency
10-
μ
F filtering capacitors are also recommended. This supply terminal is separated from the
DVDD-CORE, DVDD-3.3, PLLVDD-CORE, and AVDD-3.3 terminals internal to the device
to provide noise isolation. The DVDD-3.3 terminals must be tied together at a
low-impedance point on the circuit board. The PLLVDD-3.3, AVDD-3.3, and DVDD-3.3
terminals must be tied together with a low dc impedance connection.
RESETz
CMOS
75
G2
I
Logic reset input. Asserting this terminal low resets the internal logic. An internal pullup
resistor to VDD is provided so only an external delay capacitor is required for proper
power-up operation (see
power-up reset
in the
APPLICATIONS INFORMATION
section).
The RESETz terminal also incorporates an internal pulldown which is activated when the
PD input is asserted high. This input is otherwise a standard logic input, and can also be
driven by an open-drain type driver.
R0
R1
Bias
23
22
H9
J10
Current setting resistor terminals. These terminals are connected to a precision external
resistance to set the internal operating currents and cable driver output currents. A
resistance of 6.34 k
±
1% is required to meet the IEEE Std 1394-1995 output voltage limits.
Test control input. This input is used in the manufacturing test of the TSB41BA3A. For
normal use this terminal must be pulled low either through a 1-k
resistor to GND or directly
to GND.
SE
CMOS
35
D10
I
SLPEN
CMOS
79
J1
I
Automotive sleep mode enable input. This terminal enables the automotive sleep mode.
When deasserted (logic low), normal 1394.b functionality is maintained.
SM
CMOS
36
D9
I
Test control input. This input is used in the manufacturing test of the TSB41BA3A. For
normal use this terminal must be pulled low either through a 1-k
resistor to GND or directly
to GND.
S2_PC0
S1_PC1
S0_PC2
CMOS
66
67
68
D3
E1
E2
I
Port sleep/mode selection terminals 20 and power class programming. On hardware
reset, this terminal when used with the other 5 selection pins allows the user to select the
speed and mode of the ports. See Table 1. Depending on the selection these inputs may set
the default value of the power class indicated during self-ID.
Programming is done by tying the terminals high through a 1-k
or smaller resistor or by
tying directly to ground through a 1-k
or smaller resistor. Bus holders are built into these
terminals.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| TSB41BA3AIPFP | 功能描述:緩沖器和線路驅動器 Three-Port Cable Xcvr/Arbiter RoHS:否 制造商:Micrel 輸入線路數(shù)量:1 輸出線路數(shù)量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel |
| TSB41BA3APFP | 功能描述:緩沖器和線路驅動器 Three-Port Cable Xcvr/Arbiter RoHS:否 制造商:Micrel 輸入線路數(shù)量:1 輸出線路數(shù)量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel |
| TSB41BA3APFPG4 | 功能描述:1394 接口集成電路 Three-Port Cable Xcvr/Arbiter RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB41BA3ATPFPEP | 功能描述:緩沖器和線路驅動器 Mil Enh 3-Port Cable Xcvr/Arbiter RoHS:否 制造商:Micrel 輸入線路數(shù)量:1 輸出線路數(shù)量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel |
| TSB41BA3B | 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER |
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