參數(shù)資料
型號： TSB41BA3AIGGM
廠商： Texas Instruments, Inc.
英文描述： IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER
中文描述： 的IEEE 1394b三端口電纜收發(fā)器/仲裁者
文件頁數(shù)： 47/66頁
文件大?。?/td> 895K
代理商： TSB41BA3AIGGM
SLLS618B JUNE 2004 REVISED AUGUST 2004
47
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION (1394a-2000 INTERFACE)
interface reset and disable (continued)
The LLC requests that the interface be reset by deasserting the LPS signal and terminating all bus and request
activity. When the PHY observes that LPS has been deasserted for T
LPS_RESET
, it resets the interface. When
the interface is in the reset state, the PHY sets its CTL and D outputs in the logic 0 state and ignores any activity
on the LREQ signal. Figure 19 shows the timing for interface reset.
PCLK
(a)
(c)
(b)
CTL0, CTL1
D0 D7
LREQ
LPS
(d)
TLPS_RESET
TRESTORE
Figure 19. Interface Reset
The sequence of events for resetting the PHY-LLC interface is as follows:
(a) Normal operation. Interface is operating normally, with LPS asserted, PCLK active, status and packet data
reception and transmission via the CTL and D lines, and request activity via the LREQ line. In the above
diagram, the LPS signal is shown as a nonpulsed level signal. However, it is permissible to use a pulsed
signal for LPS in a direct connection between the PHY and LLC; a pulsed signal is required when using an
isolation barrier.
(b) LPS deasserted. The LLC deasserts the LPS signal and, within 1.0
μ
s, terminates any request or interface
bus activity, places its CTL and D outputs into a high-impedance state, and drives its LREQ output low.
(c) Interface reset. After T
LPS_RESET
time, the PHY determines that LPS is inactive, terminates any interface
bus activity, and drives its CTL and D outputs low. The PHY-LLC interface is now in the reset state.
(d) Interface restored. After the minimum T
RESTORE
time, the LLC may again assert LPS active. When LPS
is asserted, the interface is initialized as described below.
If the LLC continues to keep the LPS signal deasserted, it then requests that the interface be disabled. The PHY
disables the interface when it observes that LPS has been deasserted for T
LPS_DISABLE
. When the interface
is disabled, the PHY sets its CTL and D outputs as stated above for interface reset, but also stops PCLK activity.
The interface is also placed into the disabled condition upon a hardware reset of the PHY. Figure 20 shows the
timing for the interface disable.
When the interface is disabled, the PHY enters a low-power state if none of its ports are active.
相關(guān)PDF資料
PDF描述
TSC2100IDAR PROGRAMMABLE TOUCH SCREEN CONTROLLER WITH INTEGRATED STEREO AUDIO CODEC AND HEADPHONE/SPEAKER AMPLIFIER
TSC2300IPAGR PROGRAMMABLE TOUCH SCREEN CONTROLLER WITH AUDIO CODEC
TSC2301IGQZ PROGRAMMABLE TOUCH SCREEN CONTROLLER WITH STEREO AUDIO CODEC
TSC2301PAG SIGN, EYE PROTECTION MUST BE WORN; RoHS Compliant: NA
TSC2301PAGR PROGRAMMABLE TOUCH SCREEN CONTROLLER WITH STEREO AUDIO CODEC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TSB41BA3AIPFP 功能描述:緩沖器和線路驅(qū)動器 Three-Port Cable Xcvr/Arbiter RoHS:否 制造商:Micrel 輸入線路數(shù)量:1 輸出線路數(shù)量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel
TSB41BA3APFP 功能描述:緩沖器和線路驅(qū)動器 Three-Port Cable Xcvr/Arbiter RoHS:否 制造商:Micrel 輸入線路數(shù)量:1 輸出線路數(shù)量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel
TSB41BA3APFPG4 功能描述:1394 接口集成電路 Three-Port Cable Xcvr/Arbiter RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray
TSB41BA3ATPFPEP 功能描述:緩沖器和線路驅(qū)動器 Mil Enh 3-Port Cable Xcvr/Arbiter RoHS:否 制造商:Micrel 輸入線路數(shù)量:1 輸出線路數(shù)量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel
TSB41BA3B 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*