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參數資料
| 型號： | TSB41BA3AIGGM |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER |
| 中文描述： | 的IEEE 1394b三端口電纜收發(fā)器/仲裁者 |
| 文件頁數： | 39/66頁 |
| 文件大?。?/td> | 895K |
| 代理商： | TSB41BA3AIGGM |
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SLLS618B JUNE 2004 REVISED AUGUST 2004
39
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION (1394a-2000 INTERFACE)
LLC service request (continued)
NOTE:
The TSB41BA3A accepts a bus request with an invalid speed code and processes the bus request
normally. However, during packet transmission for such a request, the TSB41BA3A ignores any
data presented by the LLC and transmits a null packet.
For a read register request, the length of the LREQ bit stream is 9 bits as shown in Table 17.
Table 17. Read Register Request
BIT(s)
NAME
DESCRIPTION
0
Start bit
Indicates the beginning of the transfer (always 1)
13
Request type
A 100 indicating this is a read register request.
47
Address
Identifies the address of the PHY register to be read
8
Stop bit
Indicates the end of the transfer (always 0)
For a write register request, the length of the LREQ bit stream is 17 bits as shown in Table 18.
Table 18. Write Register Request
BIT(s)
NAME
DESCRIPTION
0
Start bit
Indicates the beginning of the transfer (always 1)
13
Request type
A 101 indicating this is a write register request.
47
Address
Identifies the address of the PHY register to be written to
815
Data
Gives the data that is to be written to the specified register address
16
Stop bit
Indicates the end of the transfer (always 0)
For an acceleration control request, the length of the LREQ data stream is 6 bits as shown in Table 19.
Table 19. Acceleration Control Request
BIT(s)
NAME
DESCRIPTION
0
Start bit
Indicates the beginning of the transfer (always 1)
13
Request type
A 110 indicating this is an acceleration control request.
4
Control
Asynchronous period arbitration acceleration is enabled if 1 and disabled if 0
5
Stop bIt
Indicates the end of the transfer (always 0)
For fair or priority access, the LLC sends the bus request (FairReq or PriReq) at least one clock after the
PHY-LLC interface becomes idle. If the CTL terminals are asserted to the receive state (10b) by the PHY, then
any pending fair or priority request is lost (cleared). Additionally, the PHY ignores any fair or priority requests
if the receive state is asserted while the LLC is sending the request. The LLC may then reissue the request one
clock after the next interface idle.
The cycle master node uses a priority bus request (PriReq) to send a cycle start message. After receiving or
transmitting a cycle start message, the LLC can issue an isochronous bus request (IsoReq). The PHY clears
an isochronous request only when the serial bus has been won.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| TSB41BA3AIPFP | 功能描述:緩沖器和線路驅動器 Three-Port Cable Xcvr/Arbiter RoHS:否 制造商:Micrel 輸入線路數量:1 輸出線路數量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel |
| TSB41BA3APFP | 功能描述:緩沖器和線路驅動器 Three-Port Cable Xcvr/Arbiter RoHS:否 制造商:Micrel 輸入線路數量:1 輸出線路數量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel |
| TSB41BA3APFPG4 | 功能描述:1394 接口集成電路 Three-Port Cable Xcvr/Arbiter RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB41BA3ATPFPEP | 功能描述:緩沖器和線路驅動器 Mil Enh 3-Port Cable Xcvr/Arbiter RoHS:否 制造商:Micrel 輸入線路數量:1 輸出線路數量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel |
| TSB41BA3B | 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER |
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