參數(shù)資料
型號: TSB41BA3AIGGM
廠商: Texas Instruments, Inc.
英文描述: IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER
中文描述: 的IEEE 1394b三端口電纜收發(fā)器/仲裁者
文件頁數(shù): 33/66頁
文件大小: 895K
代理商: TSB41BA3AIGGM
SLLS618B JUNE 2004 REVISED AUGUST 2004
33
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
crystal selection (continued)
NOTE:
The total frequency variation must be kept below
±
100 ppm from nominal with some allowance for
error introduced by board and device variations. Trade-offs between frequency tolerance and
stability may be made as long as the total frequency variation is less than
±
100 ppm. For example,
the frequency tolerance of the crystal may be specified at 50 ppm and the temperature tolerance
may be specified at 30 ppm to give a total of 80 ppm possible variation due to the oscillator alone.
Aging also contributes to the frequency variation.
Load capacitance: For parallel resonant mode crystal circuits, the frequency of oscillation is dependent
upon the load capacitance specified for the crystal. Total load capacitance (C
L
) is a function of not only the
discrete load capacitors, but also board layout and circuit. It may be necessary to iteratively select discrete
load capacitors until the PCLK output is within specification. It is recommended that load capacitors with
a maximum of
±
5% tolerance be used.
As an example, for the OHCI + 41LV03 evaluation module (EVM) which uses a crystal specified for 12-pF
loading, load capacitors (C9 and C10 in Figure 10) of 16 pF each were appropriate for the layout of that particular
board. The load specified for the crystal includes the load capacitors (C9, C10), the loading of the PHY terminals
(C
PHY
), and the loading of the board itself (C
BD
). The value of C
PHY
is typically about 1 pF and C
BD
is typically
0.8 pF per centimeter of board etch; a typical board can have 3 pF to 6 pF or more. The load capacitors C9 and
C10 combine as capacitors in series so that the total load capacitance is:
C
L
C9
C9
C10
C10
C
PHY
C
BD
X1
49.152 MHz
IS
X1
CPHY + CBD
X0
C10
C9
Figure 10. Load Capacitance for the TSB41BA3A PHY
NOTE:
The layout of the crystal portion of the PHY circuit is important for obtaining the correct frequency,
minimizing noise introduced into the PHY’s phase lock loop, and minimizing any emissions from
the circuit. The crystal and two load capacitors must be considered as a unit during layout. The
crystal and load capacitors must be placed as close as possible to one another while minimizing
the loop area created by the combination of the three components. Varying the size of the capacitors
may help in this. Minimizing the loop area minimizes the effect of the resonant current (I
S
) that flows
in this resonant circuit. This layout unit (crystal and load capacitors) must then be placed as close
as possible to the PHY XI and XO terminals to minimize trace lengths.
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