
SLLS618B JUNE 2004 REVISED AUGUST 2004
32
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
power-up reset
To ensure proper operation of the TSB41BA3A the RESETz terminal must be asserted low for a minimum of
2 ms from the time that PHY power reaches the minimum required supply voltage and the input clock to the PHY
is valid. When using a passive capacitor on the RESETz terminal to generate a power-on reset signal, the
minimum reset time is assured if the value of the capacitor satisfies the following equation (the value must be
no smaller than approximately 0.1
μ
F):
C
min
= 0.0077 x T + 0.085 + (external_oscillator_start-up_time x 0.05)
Where C
min
is the minimum capacitance on the RESETz terminal in
μ
F, T is the V
DD
ramp time, 10%–90%, in
ms, external_oscillator_start-up_time is the time from power applied to the external oscillator until the oscillator
outputs a valid clock in ms. If a crystal is used rather than an oscillator, then the external_oscillator_start-up_time
may be set to 0.
For example with a 2-ms power ramp time and a 2-ms oscillator startup time:
C
min
= 0.0077 x 2 + 0.085 + (2 x 0.05) = 0.2
μ
F
It is appropriate to select the nearest standard value capacitor that exceeds this value, for example 0.22
μ
F.
Or with a 2-ms power ramp time and a 49.152-MHz fundamental crystal:
C
min
= 0.0077 x 2 + 0.085 + (0 x 0.05) = 0.1
μ
F
crystal selection
The TSB41BA3A and other Texas Instruments PHY devices are designed to use an external 49.152-MHz
crystal connected between the XI and XO terminals to provide the reference for an internal oscillator circuit. This
oscillator in turn drives a PLL circuit that generates the various clocks required for transmission and
resynchronization of data at the S100 through S400 media data rates.
A variation of less than
±
100 ppm from nominal for the media data rates is required by IEEE Std 1394. Adjacent
PHYs may therefore have a difference of up to 200 ppm from each other in their internal clocks, and PHYs must
be able to compensate for this difference over the maximum packet length. Larger clock variations may cause
resynchronization overflows or underflows, resulting in corrupted packet data or even PHY lockup.
For the TSB41BA3A, the PCLK output may be used to measure the frequency accuracy and stability of the
internal oscillator and PLL from which it is derived. When operating the PHY-LLC interface with a non-1394b
LLC, the frequency of the PCLK output must be within
±
100 ppm of the nominal frequency of 49.152 MHz. When
operating the PHY-LLC interface with a 1394b LLC, the frequency of the PCLK output must be within
±
100 ppm
of the nominal frequency of 98.304 MHz.
The following are some typical specifications for crystals used with the physical layers from Texas Instruments
in order to achieve the required frequency accuracy and stability:
Crystal mode of operation: Fundamental
Frequency tolerance at 25 C: Total frequency variation for the complete circuit is
±
100 ppm. A crystal with
±
30 ppm frequency tolerance is recommended for adequate margin.
Frequency stability (over temperature and age): A crystal with
±
30 ppm frequency stability is recommended
for adequate margin.