參數(shù)資料
型號： TMS320SP5410AGGU12
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： Fixed-Point Digital Signal Processor
中文描述： 定點數(shù)字信號處理器
文件頁數(shù)： 75/100頁
文件大?。?/td> 913K
代理商： TMS320SP5410AGGU12
www.ti.com
5.11
Reset, BIO, Interrupt, and MP/MC Timings
BIO
CLKOUT
RS, INTn, NMI
X2/CLKIN
t
h(BIO)
t
h(RS)
t
su(INT)
t
w(BIO)S
t
su(BIO)
t
w(RSL)
t
su(RS)
TMS320VC5410A
Fixed-Point Digital Signal Processor
SPRS139G–NOVEMBER 2000–REVISED JANUARY 2005
Table 5-17 assumes testing over recommended operating conditions and H = 0.5t
c(CO)
(see Figure 5-15,
Figure 5-16, and Figure 5-17).
Table 5-17. Reset, BIO, Interrupt, and MP/MC Timing Requirements
5410A-120
5410A-160
MIN
2
4
1
4
4H+3
2H+3
4H
2H+2
4H
2H+2
4H
7
3
7
7
5
UNIT
MAX
t
h(RS)
t
h(BIO)
t
h(INT)
t
h(MPMC)
t
w(RSL)
t
w(BIO)S
t
w(BIO)A
t
w(INTH)S
t
w(INTH)A
t
w(INTL)S
t
w(INTL)A
t
w(INTL)WKP
t
su(RS)
t
su(BIO)
t
su(INT)
t
su(MPMC)
(1)
The external interrupts (INT0–INT3, NMI) are synchronized to the core CPU by way of a two-flip-flop synchronizer that samples these
inputs with consecutive falling edges of CLKOUT. The input to the interrupt pins is required to represent a 1-0-0 sequence at the timing
that is corresponding to three CLKOUTs sampling sequence.
(2)
If the PLL mode is selected, then at power-on sequence, or at wakeup from IDLE3, RS must be held low for at least 50 μs to ensure
synchronization and lock-in of the PLL.
(3)
Note that RS may cause a change in clock frequency, therefore changing the value of H.
(4)
The diagram assumes clock mode is divide-by-2 and the CLKOUT divide factor is set to no-divide mode (DIVFCT=00 field in the BSCR).
Hold time, RS after CLKOUT low
Hold time, BIO after CLKOUT low
Hold time, INTn, NMI, after CLKOUT low
(1)
Hold time, MP/MC after CLKOUT low
Pulse duration, RS low
(2)(3)
Pulse duration, BIO low, synchronous
Pulse duration, BIO low, asynchronous
Pulse duration, INTn, NMI high (synchronous)
Pulse duration, INTn, NMI high (asynchronous)
Pulse duration, INTn, NMI low (synchronous)
Pulse duration, INTn, NMI low (asynchronous)
Pulse duration, INTn, NMI low for IDLE2/IDLE3 wakeup
Setup time, RS before X2/CLKIN low
(4)
Setup time, BIO before CLKOUT low
Setup time, INTn, NMI, RS before CLKOUT low
Setup time, MP/MC before CLKOUT low
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figure 5-15. Reset and BIO Timings
Electrical Specifications
75
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