參數(shù)資料
型號(hào)： TMS320SP5410AGGU12
廠商： Texas Instruments, Inc.
元件分類(lèi)： 數(shù)字信號(hào)處理
英文描述： Fixed-Point Digital Signal Processor
中文描述： 定點(diǎn)數(shù)字信號(hào)處理器
文件頁(yè)數(shù)： 61/100頁(yè)
文件大?。?/td> 913K
代理商： TMS320SP5410AGGU12
www.ti.com
5.7.2
Multiply-By-N Clock Option (PLL Enabled)
TMS320VC5410A
Fixed-Point Digital Signal Processor
SPRS139G–NOVEMBER 2000–REVISED JANUARY 2005
The frequency of the reference clock provided at the X2/CLKIN pin can be multiplied by a factor of N to
generate the internal machine cycle. The selection of the clock mode and the value of N is described in
Section Section 3.6. Following reset, the software PLL can be programmed for the desired multiplication
factor. Refer to the
TMS320C54x DSP Reference Set
,
Volume 1: CPU and Peripherals
(literature number
SPRU131) for detailed information on programming the PLL.
When an external clock source is used, the external frequency injected must conform to specifications
listed in Table 5-5.
Table 5-5 and Table 5-6 assume testing over recommended operating conditions and H = 0.5t
c(CO)
(see
Figure 5-4).
Table 5-5. Multiply-By-N Clock Option Timing Requirements
5410A-120
5410A-160
MIN
UNIT
MAX
Integer PLL multiplier N (N =
1–15)
(1)
PLL multiplier N = x.5
(1)
PLL multiplier N = x.25, x.75
(1)
20
200
t
c(CI)
Cycle time, X2/CLKIN
ns
20
20
100
50
t
f(CI)
t
r(CI)
t
w(CIL)
t
w(CIH)
(1)
Fall time, X2/CLKIN
Rise time, X2/CLKIN
Pulse duration, X2/CLKIN low
Pulse duration, X2/CLKIN high
4
4
ns
ns
ns
ns
4
4
N is the multiplication factor.
Table 5-6. Multiply-By-N Clock Option Switching Characteristics
5410A-120
MIN
8.33
4
5410A-160
MIN
6.25
4
PARAMETER
UNIT
TYP
MAX
TYP
MAX
t
c(CO)
t
d(CI-CO)
t
f(CO)
t
r(CO)
t
w(COL)
t
w(COH)
t
p
Cycle time, CLKOUT
Delay time, X2/CLKIN high/low to CLKOUT high/low
Fall time, CLKOUT
Rise time, CLKOUT
Pulse duration, CLKOUT low
Pulse duration, CLKOUT high
Transitory phase, PLL lock-up time
ns
ns
ns
ns
ns
ns
ms
7
2
2
H
H
11
7
2
2
H
H
11
30
30
61
Electrical Specifications
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