參數(shù)資料
型號(hào)： TMS320SP5410AGGU12
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： Fixed-Point Digital Signal Processor
中文描述： 定點(diǎn)數(shù)字信號(hào)處理器
文件頁數(shù)： 42/100頁
文件大?。?/td> 913K
代理商： TMS320SP5410AGGU12
www.ti.com
3.8.7
DMA in Autoinitialization Mode
3.8.8
DMA Transfer Counting
TMS320VC5410A
Fixed-Point Digital Signal Processor
SPRS139G–NOVEMBER 2000–REVISED JANUARY 2005
The DMA can automatically reinitialize itself after completion of a block transfer. Some of the DMA
registers can be preloaded for the next block transfer through the DMA reload registers (DMGSA,
DMGDA, DMGCR, and DMGFR). Autoinitialization allows:
Continuous operation:Normally, the CPU would have to reinitialize the DMA immediately after the
completion of the current block transfers, but with the reload registers, it can reinitialize these values
for the next block transfer any time after the current block transfer begins.
Repetitive operation:The CPU does not preload the reload register with new values for each block
transfer but only loads them on the first block transfer.
The 5410A DMA has been enhanced to expand the DMA reload register sets. Each DMA channel now
has its own DMA reload register set. For example, the DMA reload register set for channel 0 has
DMGSA0, DMGDA0, DMGCR0, and DMGFR0 while DMA channel 1 has DMGSA1, DMGDA1, DMGCR1,
and DMGFR1, etc.
To utilize the additional DMA reload registers, the AUTOIX bit is added to the DMPREC register as shown
in Figure 3-22.
15
14
13
8
FREE
AUTOIX
DPRC[5:0]
7
6
5
0
INTOSEL
DE[5:0]
LEGEND: R = Read, W = Write, n = value at reset
Figure 3-22. DMPREC Register
Table 3-13. DMA Reload Register Selection
AUTOIX
0 (default)
1
DMA RELOAD REGISTER USAGE IN AUTO INIT MODE
All DMA channels use DMGSA0, DMGDA0, DMGCR0 and DMGFR0
Each DMA channel uses its own set of reload registers
The DMA channel element count register (DMCTRx) and the frame count register (DMFRCx) contain bit
fields that represent the number of frames and the number of elements per frame to be transferred.
Frame count. This 8-bit value defines the total number of frames in the block transfer. The maximum
number of frames per block transfer is 128 (FRAME COUNT= 0FFh). The counter is decremented
upon the last read transfer in a frame transfer. Once the last frame is transferred, the selected 8-bit
counter is reloaded with the DMA global frame reload register (DMGFR) if the AUTOINIT bit is set to 1.
A frame count of 0 (default value) means the block transfer contains a single frame.
Element count. This 16-bit value defines the number of elements per frame. This counter is
decremented after the read transfer of each element. The maximum number of elements per frame is
65536(DMCTRn = 0FFFFh). In autoinitialization mode, once the last frame is transferred, the counter
is reloaded with the DMA global count reload register (DMGCR).
42
Functional Overview
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