參數(shù)資料
型號: TMS320SP5410AGGU12
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號處理
英文描述: Fixed-Point Digital Signal Processor
中文描述: 定點(diǎn)數(shù)字信號處理器
文件頁數(shù): 23/100頁
文件大小: 913K
代理商: TMS320SP5410AGGU12
www.ti.com
3.2.1
Software-Programmable Wait-State Generator
TMS320VC5410A
Fixed-Point Digital Signal Processor
SPRS139G–NOVEMBER 2000–REVISED JANUARY 2005
The software wait-state generator of the 5410A can extend external bus cycles by up to fourteen machine
cycles. Devices that require more than fourteen wait states can be interfaced using the hardware READY
line. When all external accesses are configured for zero wait states, the internal clocks to the wait-state
generator are automatically disabled. Disabling the wait-state generator clocks reduces the power
consumption of the 5410A.
The software wait-state register (SWWSR) controls the operation of the wait-state generator. The 14 LSBs
of the SWWSR specify the number of wait states (0 to 7) to be inserted for external memory accesses to
five separate address ranges. This allows a different number of wait states for each of the five address
ranges. Additionally, the software wait-state multiplier (SWSM) bit of the software wait-state control
register (SWCR) defines a multiplication factor of 1 or 2 for the number of wait states. At reset, the
wait-state generator is initialized to provide seven wait states on all external memory accesses. The
SWWSR bit fields are shown in Figure 3-5 and described in Table 3-3.
15
XPA
14
12
11
9
8
I/O
DATA
DATA
R/W-0
R/W-111
R/W-111
7
6
5
3
2
0
DATA
PROGRAM
PROGRAM
R/W-111
R/W-111
R/W-111
LEGEND: R = Read, W = Write, n = value at reset
Figure 3-5. Software Wait-State Register (SWWSR) [Memory-Mapped Register (MMR) Address
0028h]
Table 3-3. Software Wait-State Register (SWWSR) Field Descriptions
BIT
FIELD
VALUE
DESCRIPTION
Extended program address control bit. XPA is used in conjunction with the program space fields (bits 0
through 5) to select the address range for program space wait states.
I/O space. The field value (0-7) corresponds to the base number of wait states for I/O space accesses
within addresses 0000-FFFFh. The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for
the base number of wait states.
Upper data space. The field value (0-7) corresponds to the base number of wait states for external
data space accesses within addresses 8000-FFFFh. The SWSM bit of the SWCR defines a
multiplication factor of 1 or 2 for the base number of wait states.
Lower data space. The field value (0-7) corresponds to the base number of wait states for external
data space accesses within addresses 0000-7FFFh. The SWSM bit of the SWCR defines a
multiplication factor of 1 or 2 for the base number of wait states.
Upper program space. The field value (0-7) corresponds to the base number of wait states for external
program space accesses within the following addresses:
XPA = 0: xx8000 - xxFFFFh
XPA = 1: 400000h - 7FFFFFh
The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states.
Program space. The field value (0-7) corresponds to the base number of wait states for external
program space accesses within the following addresses:
XPA = 0: xx0000 - xx7FFFh
XPA = 1: 000000 - 3FFFFFh
The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states.
15
XPA
0
14-12
I/O
111
11-9
Data
111
8-6
Data
111
5-3
Program
111
2-0
Program
111
Functional Overview
23
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