參數(shù)資料
型號(hào)： TMS320SP5410AGGU12
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： Fixed-Point Digital Signal Processor
中文描述： 定點(diǎn)數(shù)字信號(hào)處理器
文件頁數(shù)： 49/100頁
文件大?。?/td> 913K
代理商： TMS320SP5410AGGU12
www.ti.com
3.12
McBSP Control Registers and Subaddresses
TMS320VC5410A
Fixed-Point Digital Signal Processor
SPRS139G–NOVEMBER 2000–REVISED JANUARY 2005
The control registers for the multichannel buffered serial port (McBSP) are accessed using the subbank
addressing scheme. This allows a set or subbank of registers to be accessed through a single memory
location. The McBSP subbank address register (SPSA) is used as a pointer to select a particular register
within the subbank. The McBSP data register (SPSDx) is used to access (read or write) the selected
register. Table 3-19 shows the McBSP control registers and their corresponding subaddresses.
Table 3-19. McBSP Control Registers and Subaddresses
McBSP0
McBSP1
McBSP2
SUB-
DESCRIPTION
ADDRESS
NAME
SPCR10
SPCR20
RCR10
RCR20
XCR10
XCR20
SRGR10
SRGR20
MCR10
MCR20
RCERA0
RCERB0
XCERA0
XCERB0
PCR0
ADDRESS
39h
39h
39h
39h
39h
39h
39h
39h
39h
39h
39h
39h
39h
39h
39h
NAME
SPCR11
SPCR21
RCR11
RCR21
XCR11
XCR21
SRGR11
SRGR21
MCR11
MCR21
RCERA1
RCERB1
XCERA1
XCERB1
PCR1
ADDRESS
49h
49h
49h
49h
49h
49h
49h
49h
49h
49h
49h
49h
49h
49h
49h
NAME
SPCR12
SPCR22
RCR12
RCR22
XCR12
XCR22
SRGR12
SRGR22
MCR12
MCR22
RCERA2
RCERA2
XCERA2
XCERA2
PCR2
ADDRESS
35h
35h
35h
35h
35h
35h
35h
35h
35h
35h
35h
35h
35h
35h
35h
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
Serial port control register 1
Serial port control register 2
Receive control register 1
Receive control register 2
Transmit control register 1
Transmit control register 2
Sample rate generator register 1
Sample rate generator register 2
Multichannel control register 1
Multichannel control register 2
Receive channel enable register partition A
Receive channel enable register partition B
Transmit channel enable register partition A
Transmit channel enable register partition B
Pin control register
Additional channel enable register for
128-channel selection
Additional channel enable register for
128-channel selection
Additional channel enable register for
128-channel selection
Additional channel enable register for
128-channel selection
Additional channel enable register for
128-channel selection
Additional channel enable register for
128-channel selection
Additional channel enable register for
128-channel selection
Additional channel enable register for
128-channel selection
Additional channel enable register for
128-channel selection
Additional channel enable register for
128-channel selection
Additional channel enable register for
128-channel selection
Additional channel enable register for
128-channel selection
RCERC0
39h
RCERC1
49h
RCERC2
35h
010h
RCERD0
39h
RCERD1
49h
RCERD2
35h
011h
XCERC0
39h
XCERC1
49h
XCERC2
35h
012h
XCERD0
39h
XCERD1
49h
XCERD2
35h
013h
RCERE0
39h
RCERE1
49h
RCERE2
35h
014h
RCERF0
39h
RCERF1
49h
RCERF2
35h
015h
XCERE0
39h
XCERE1
49h
XCERE2
35h
016h
XCERF0
39h
XCERF1
49h
XCERF2
35h
017h
RCERG0
39h
RCERG1
49h
RCERG2
35h
018h
RCERH0
39h
RCERH1
49h
RCERH2
35h
019h
XCERG0
39h
XCERG1
49h
XCERG2
35h
01Ah
XCERH0
39h
XCERH1
49h
XCERH2
35h
01Bh
Functional Overview
49
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