參數(shù)資料
型號: TMS320SP5410AGGU12
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號處理
英文描述: Fixed-Point Digital Signal Processor
中文描述: 定點數(shù)字信號處理器
文件頁數(shù): 25/100頁
文件大?。?/td> 913K
代理商: TMS320SP5410AGGU12
www.ti.com
TMS320VC5410A
Fixed-Point Digital Signal Processor
SPRS139G–NOVEMBER 2000–REVISED JANUARY 2005
Table 3-5. Bank-Switching Control Register (BSCR) Field Descriptions
BIT
FIELD
VALUE
DESCRIPTION
Consecutive bank-switching
.
Specifies the bank-switching mode.
Bank-switching on 32K bank boundaries only. This bit is cleared if fast access is desired for
continuous memory reads (i.e., no starting and trailing cycles between read cycles).
Consecutive bank switches on external memory reads. Each read cycle consists of 3 cycles:
starting cycle, read cycle, and trailing cycle.
CLKOUT output divide factor
.
The CLKOUT output is driven by an on-chip source having a
frequency equal to 1/(DIVFCT+1) of the DSP clock.
CLKOUT is not divided.
CLKOUT is divided by 2 from the DSP clock.
CLKOUT is divided by 3 from the DSP clock.
CLKOUT is divided by 4 from the DSP clock (default value following reset.
IACK signal output off
.
Controls the output of the IACK signal. IACKOFF is set to 1 at reset.
The IACK signal output off function is disabled.
The IACK signal output off function is enabled.
Reserved
HPI bus holder. Controls the HPI bus holder. HBH is cleared to 0 at reset.
The bus holder is disabled except when HPI16=1.
The bus holder is enabled. When not driven, the HPI data bus, HD[7:0] is held in the previous
logic level.
Bus holder. Controls the bus holder. BH is cleared to 0 at reset.
The bus holder is disabled.
The bus holder is enabled. When not driven, the data bus, D[15:0] is held in the previous logic
level.
Reserved
0
15
CONSEC
(1)
1
00
01
10
11
14-13
DIVFCT
12
IACKOFF
0
1
11-3
Reserved
0
2
HBH
1
0
1
BH
1
0
Reserved
(1)
For additional information, see Section Section 3.7 of this document.
The 5410A has an internal register that holds the MSB of the last address used for a read or write
operation in program or data space. In the non-consecutive bank switches (CONSEC = 0), if the MSB of
the address used for the current read does not match that contained in this internal register, the MSTRB
(memory strobe) signal is not asserted for one CLKOUT cycle. During this extra cycle, the address bus
switches to the new address. The contents of the internal register are replaced with the MSB for the read
of the current address. If the MSB of the address used for the current read matches the bits in the
register, a normal read cycle occurs.
In non-consecutive bank switches (CONSEC = 0), if repeated reads are performed from the same memory
bank, no extra cycles are inserted. When a read is performed from a different memory bank, memory
conflicts are avoided by inserting an extra cycle. For more information, see Section Section 3.7 of this
document.
The bank-switching mechanism automatically inserts one extra cycle in the following cases:
A memory read followed by another memory read from a different memory bank.
A program-memory read followed by a data-memory read.
A data-memory read followed by a program-memory read.
A program-memory read followed by another program-memory read from a different page.
Functional Overview
25
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