參數(shù)資料
型號(hào)： TMS320SP5410AGGU12
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： Fixed-Point Digital Signal Processor
中文描述： 定點(diǎn)數(shù)字信號(hào)處理器
文件頁(yè)數(shù)： 21/100頁(yè)
文件大?。?/td> 913K
代理商： TMS320SP5410AGGU12
www.ti.com
Hex
010000
01FFFF
Program
Page 1
XPC=1
On-Chip
DARAM0-3
(OVLY=1)
External
(OVLY=0)
On-Chip
DARAM4-7
(MP/MC=0)
External
(MP/MC=1)
Hex
020000
Program
02FFFF
Page 2
XPC=2
On-Chip
DARAM0-3
(OVLY=1)
External
(OVLY=0)
External
Hex
Program
On-Chip
DARAM0-3
(OVLY=1)
External
(OVLY=0)
7F0000
7FFFFF
Page 127
XPC=7Fh
External
7F7FFF
7F8000
027FFF
028000
017FFF
018000
......
TMS320VC5410A
Fixed-Point Digital Signal Processor
SPRS139G–NOVEMBER 2000–REVISED JANUARY 2005
A.
Address ranges for on-chip DARAM in program memory are: DARAM4: 018000h-019FFFh; DARAM5: 01A000h-01
BFFFh DARAM6: 01C000h-01DFFFh; DARAM7: 01E000h-01FFFFh
Figure 3-3. Extended Program Memory Map
3.1.7.1
Relocatable Interrupt Vector Table
The reset, interrupt, and trap vectors are addressed in program space. These vectors are soft — meaning
that the processor, when taking the trap, loads the program counter (PC) with the trap address and
executes the code at the vector location. Four words, either two 1-word instructions or one 2-word
instruction, are reserved at each vector location to accommodate a delayed branch instruction which
allows branching to the appropriate interrupt service routine without the overhead.
At device reset, the reset, interrupt, and trap vectors are mapped to address FF80h in program space.
However, these vectors can be remapped to the beginning of any 128-word page in program space after
device reset. This is done by loading the interrupt vector pointer (IPTR) bits in the PMST register with the
appropriate 128-word page boundary address. After loading IPTR, any user interrupt or trap vector is
mapped to the new 128-word page.
NOTE
The hardware reset (RS) vector cannot be remapped because the hardware reset loads
the IPTR with 1s. Therefore, the reset vector is always fetched at location FF80h in
program space.
15
8
IPTR
R/W-1FF
7
6
5
4
3
2
1
0
IPTR
MP/MC
OVLY
AVIS
DROM
CLKOFF
SMUL
SST
R/W-MP/MC
pin
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R = Read, W = Write, n = value at reset
Figure 3-4. Processor Mode Status Register (PMST)
Functional Overview
21
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