參數(shù)資料
型號: TMS320SP5410AGGU12
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號處理
英文描述: Fixed-Point Digital Signal Processor
中文描述: 定點(diǎn)數(shù)字信號處理器
文件頁數(shù): 22/100頁
文件大?。?/td> 913K
代理商: TMS320SP5410AGGU12
www.ti.com
3.2
On-Chip Peripherals
TMS320VC5410A
Fixed-Point Digital Signal Processor
SPRS139G–NOVEMBER 2000–REVISED JANUARY 2005
Table 3-2. Processor Mode Status Register (PMST) Field Descriptions
BIT
FIELD
VALUE
DESCRIPTION
Interrupt vector pointer. The 9-bit IPTR field points to the 128-word program page where the interrupt
vectors reside. The interrupt vectors can be remapped to RAM for boot-loaded operations. At reset,
these bits are all set to 1; the reset vector always resides at address FF80h in program memory space.
The RESET instruction does not affect this field.
Microprocessor/microcomputer mode. MP/MC enables/disables the on-chip ROM to be addressable in
program memory space.
The on-chip ROM is enabled and addressable.
The on-chip ROM is not available.
MP/MC is set to the value corresponding to the logic level on the MP/MC pin when sampled at reset.
This pin is not sampled again until the next reset. The RESET instruction does not affect this bit. This
bit can also be set or cleared by software.
RAM overlay. OVLY enables on-chip dual-access data RAM blocks to be mapped into program space.
The values for the OVLY bit are:
The on-chip RAM is addressable in data space but not in program space.
The on-chip RAM is mapped into program space and data space. Data page 0 (addresses 0h to 7Fh),
however, is not mapped into program space.
Address visibility mode. AVIS enables/disables the internal program address to be visible at the
address pins.
The external address lines do not change with the internal program address. Control and data lines are
not affected and the address bus is driven with the last address on the bus.
This mode allows the internal program address to appear at the pins of the 5410A so that the internal
program address can be traced. Also, it allows the interrupt vector to be decoded in conjunction with
IACK when the interrupt vectors reside on on-chip memory.
Data ROM. DROM enables on-chip ROM to be mapped into data space. The values for the DROM bit
are:
The on-chip ROM is not mapped into data space.
A portion of the on-chip RAM is mapped into data space.
CLOCKOUT off. When the CLKOFF bit is 1, the output of CLKOUT is disabled and remains at a high
level.
Saturation on multiplication. When SMUL = 1, saturation of a multiplication result occurs before
performing the accumulation in a MAC of MAS instruction. The SMUL bit applies only when OVM = 1
and FRCT = 1.
Saturation on store. When SST = 1, saturation of the data from the accumulator is enabled before
storing in memory. The saturation is performed after the shift operation.
15-7
IPTR
1FFh
MP/MC
pin
0
1
6
MP/MC
5
OVLY
0
1
4
AVIS
0
1
3
DROM
0
1
2
CLKOFF
0
1
SMUL
0
0
SST
0
The 5410A device has the following peripherals:
Software-programmable wait-state generator
Programmable bank-switching
A host-port interface (HPI8/16)
Three multichannel buffered serial ports (McBSPs)
A hardware timer
A clock generator with a multiple phase-locked loop (PLL)
Enhanced external parallel interface (XIO2)
A DMA controller (DMA)
22
Functional Overview
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