參數(shù)資料
型號: TMS320SP5410AGGU12
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號處理
英文描述: Fixed-Point Digital Signal Processor
中文描述: 定點數(shù)字信號處理器
文件頁數(shù): 36/100頁
文件大?。?/td> 913K
代理商: TMS320SP5410AGGU12
www.ti.com
WRITE
CLKOUT
A[22:0]
D[15:0]
R/W
PS/DS/IS
Leading
Cycle
Write
Cycle
MSTRB or IOSTRB
Trailing
Cycle
TMS320VC5410A
Fixed-Point Digital Signal Processor
SPRS139G–NOVEMBER 2000–REVISED JANUARY 2005
Figure 3-17 shows the bus sequence for all memory writes and I/O writes. The accesses shown in
Figure 3-17 always require three CLKOUT cycles to complete.
Figure 3-17. Memory Write and I/O Write Bus Sequence
The enhanced interface also provides the ability for DMA transfers to extend to external memory. For
more information on DMA capability, see the DMA sections that follow.
The enhanced interface improves the low-power performance already present on the TMS320C5000
DSP platform by switching off the internal clocks to the interface when it is not being used. This
power-saving feature is automatic, requires no software setup, and causes no latency in the operation of
the interface.
Additional features integrated in the enhanced interface are the ability to automatically insert
bank-switching cycles when crossing 32K memory boundaries (see Section Section 3.2.2), the ability to
program up to 14 wait states through software (see Section Section 3.2.1), and the ability to divide down
CLKOUT by a factor of 1, 2, 3, or 4. Dividing down CLKOUT provides an alternative to wait states when
interfacing to slower external memory or peripheral devices. While inserting wait states extends the bus
sequence during read or write accesses, it does not slow down the bus signal sequences at the beginning
and the end of the access. Dividing down CLKOUT provides a method of slowing the entire bus sequence
when necessary. The CLKOUT divide-down factor is controlled through the DIVFCT field in the
bank-switching control register (BSCR) (see Table 3-5).
36
Functional Overview
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