參數(shù)資料
型號(hào)： TMS320SP5410AGGU12
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： Fixed-Point Digital Signal Processor
中文描述： 定點(diǎn)數(shù)字信號(hào)處理器
文件頁(yè)數(shù)： 44/100頁(yè)
文件大?。?/td> 913K
代理商： TMS320SP5410AGGU12
www.ti.com
3.8.12
DMA Controller Synchronization Events
TMS320VC5410A
Fixed-Point Digital Signal Processor
SPRS139G–NOVEMBER 2000–REVISED JANUARY 2005
The transfers associated with each DMA channel can be synchronized to one of several events. The
DSYN bit field of the DMSEFCn register selects the synchronization event for a channel. The list of
possible events and the DSYN values are shown in Table 3-15.
Table 3-15. DMA Synchronization Events
DSYN VALUE
0000b
0001b
0010b
0011b
0100b
0101b
0110b
0111b
1000b
1001b
1010b
1011b
1100b
1101b
1110b
1111b
DMA SYNCHRONIZATION EVENT
No synchronization used
McBSP0 receive event
McBSP0 transmit event
McBSP2 receive event
McBSP2 transmit event
McBSP1 receive event
McBSP1 transmit event
McBSP0 receive event - ABIS mode
McBSP0 transmit event - ABIS mode
McBSP2 receive event - ABIS mode
McBSP2 transmit event - ABIS mode
McBSP1 receive event - ABIS mode
McBSP1 transmit event - ABIS mode
Timer interrupt event
External interrupt 3
Reserved
The DMA controller can generate a CPU interrupt for each of the six channels. However, due to a limit on
the number of internal CPU interrupt inputs, channels 0, 1, 2, and 3 are multiplexed with other interrupt
sources. DMA channels 0, 1, 2, and 3 share an interrupt line with the receive and transmit portions of the
McBSP. When the 5410A is reset, the interrupts from these three DMA channels are deselected. The
INTOSEL bit field in the DMPREC register can be used to select these interrupts, as shown in Table 3-16.
Table 3-16. DMA Channel Interrupt Selection
INTOSEL Value
00b (reset
01b
10b
11b
IMR/IFR[6]
BRINT2
BRINT2
DMAC0
IMR/IFR[7]
BXINT2
BXINT2
DMAC1
IMR/IFR[10]
BRINT1
DMAC2
DMAC2
IMR/IFR[11]
BXINT1
DMAC3
DMAC3
Reserved
44
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