參數(shù)資料
型號： TMS320SP5410AGGU12
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： Fixed-Point Digital Signal Processor
中文描述： 定點數(shù)字信號處理器
文件頁數(shù)： 59/100頁
文件大小： 913K
代理商： TMS320SP5410AGGU12
www.ti.com
5.7
Clock Options
5.7.1
Divide-By-Two and Divide-By-Four Clock Options
TMS320VC5410A
Fixed-Point Digital Signal Processor
SPRS139G–NOVEMBER 2000–REVISED JANUARY 2005
The frequency of the reference clock provided at the CLKIN pin can be divided by a factor of two or four or
multiplied by one of several values to generate the internal machine cycle.
The frequency of the reference clock provided at the X2/CLKIN pin can be divided by a factor of two or
four to generate the internal machine cycle. The selection of the clock mode is described in Section
Section 3.6.
When an external clock source is used, the frequency injected must conform to specifications listed in
Table 5-3.
An external frequency source can be used by applying an input clock to X2/CLKIN with X1 left
unconnected.
Table 5-2 shows the configuration options for the CLKMD pins that generate the external divide-by-2 or
divide-by-4 clock option.
Table 5-2. Clock Mode Pin Settings for the Divide-By-2 and By Divide-By-4 Clock Options
CLKMD1
0
1
1
CLKMD2
0
0
1
CLKMD3
0
1
1
Clock Mode
1/2, PLL disabled
1/4, PLL disabled
1/2, PLL disabled
Table 5-3 and Table 5-4 assume testing over recommended operating conditions and H = 0.5t
c(CO)
(see
Figure 5-3).
Table 5-3. Divide-By-2 and Divide-By-4 Clock Options Timing Requirements
5410A-120
5410A-160
MIN
20
UNIT
MAX
t
c(CI)
t
f(CI)
t
r(CI)
t
w(CIL)
t
w(CIH)
Cycle time, X2/CLKIN
Fall time, X2/CLKIN
Rise time, X2/CLKIN
Pulse duration, X2/CLKIN low
Pulse duration, X2/CLKIN high
ns
ns
ns
ns
ns
4
4
4
4
Table 5-4. Divide-By-2 and Divide-By-4 Clock Options Switching Characteristics
5410A-120
MIN
8.33
(1)
4
5410A-160
MIN
6.25
(1)
4
Parameter
UNIT
TYP
MAX
TYP
MAX
t
c(CO)
t
d(CIH-CO)
t
f(CO)
t
r(CO)
t
w(COL)
Cycle time, CLKOUT
Delay time, X2/CLKIN high to CLKOUT high/low
Fall time, CLKOUT
Rise time, CLKOUT
Pulse duration, CLKOUT low
(2)
(2)
ns
ns
ns
ns
ns
7
1
1
H
11
7
1
1
H
11
H –3
H + 3
H –3
H + 3
(1)
(2)
It is recommended that the PLL clocking option be used for maximum frequency operation.
This device utilizes a fully static design and therefore can operate with t
c(CI)
approaching
∞
. The device is characterized at frequencies
approaching 0 Hz.
Electrical Specifications
59
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