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TMS320VC5410A
Fixed-Point Digital Signal Processor
SPRS139G–NOVEMBER 2000–REVISED JANUARY 2005
List of Figures
2-1
144-Ball GGU MicroStar BGA (Bottom View)
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10
144-Pin PGE Low-Profile Quad Flatpack (Top View)
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12
TMS320VC5410A Functional Block Diagram
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17
Program and Data Memory Map
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20
Extended Program Memory Map
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21
Processor Mode Status Register (PMST)
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21
Software Wait-State Register (SWWSR) [Memory-Mapped Register (MMR) Address 0028h]
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23
Software Wait-State Control Register (SWCR) [MMR Address 002Bh]
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24
Bank-Switching Control Register (BSCR) [MMR Address 0029h]
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24
Host-Port Interface — Nonmultiplexed Mode
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27
HPI Memory Map
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28
Pin Control Register (PCR)
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29
Multichannel Control Register 2x (MCR2x)
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30
Multichannel Control Register 1x (MCR1x)
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31
Receive Channel Enable Registers Bit Layout for Partitions A to H
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31
Transmit Channel Enable Registers Bit Layout for Partitions A to H
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31
Nonconsecutive Memory Read and I/O Read Bus Sequence
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34
Consecutive Memory Read Bus Sequence (n = 3 reads)
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35
Memory Write and I/O Write Bus Sequence
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36
DMA Transfer Mode Control Register (DMMCRn)
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37
DMA Channel Enable Control Register (DMCECTL)
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39
On-Chip DMA Memory Map for Program Space (DLAXS = 0 and SLAXS = 0)
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40
On-Chip DMA Memory Map for Data and IO Space (DLAXS = 0 and SLAXS = 0)
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41
DMPREC Register
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42
General-Purpose I/O Control Register (GPIOCR) [MMR Address 003Ch]
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45
General-Purpose I/O Status Register (GPIOSR) [MMR Address 003Dh]
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45
Device ID Register (CSIDR) [MMR Address 003Eh]
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46
IFR and IMR
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52
Tester Pin Electronics
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57
Internal Divide-By-Two Clock Option With External Crystal
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58
External Divide-By-Two Clock Timing
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60
Multiply-By-One Clock Timing
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62
Nonconsecutive Mode Memory Reads
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63
Consecutive Mode Memory Reads
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64
Memory Write (MSTRB = 0)
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66
Parallel I/O Port Read (IOSTRB = 0)
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68
Parallel I/O Port Write (IOSTRB = 0)
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69
Memory Read With Externally Generated Wait States
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71
Memory Write With Externally Generated Wait States
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71
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List of Figures
5