參數(shù)資料
型號(hào)： TMS320SP5410AGGU12
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： Fixed-Point Digital Signal Processor
中文描述： 定點(diǎn)數(shù)字信號(hào)處理器
文件頁數(shù)： 48/100頁
文件大?。?/td> 913K
代理商： TMS320SP5410AGGU12
www.ti.com
TMS320VC5410A
Fixed-Point Digital Signal Processor
SPRS139G–NOVEMBER 2000–REVISED JANUARY 2005
Table 3-18. Peripheral Memory-Mapped Registers for Each DSP Subsystem
ADDRESS
DEC
32
33
34
35
36
37
38
39
40
41
42
43
44
45-47
48
49
50
51
52
53
54-55
56
57
58-59
60
61
62
63
64
65
66
67
68-71
72
73
74-83
84
85
86
87
88
89-95
NAME
DESCRIPTION
HEX
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D-2F
30
31
32
33
34
35
36-37
38
39
3A-3B
3C
3D
3E
3F
40
41
42
43
44-47
48
49
4A-53
54
55
56
57
58
59-5F
DRR20
DRR10
DXR20
DXR10
TIM
PRD
TCR
—
SWWSR
BSCR
—
SWCR
HPIC
—
DRR22
DRR12
DXR22
DXR12
SPSA2
SPSD2
—
SPSA0
SPSD0
—
GPIOCR
GPIOSR
CSIDR
—
DRR21
DRR11
DXR21
DXR11
—
SPSA1
SPSD1
—
DMPREC
DMSA
DMSDI
DMSDN
CLKMD
—
McBSP 0 Data Receive Register 2
McBSP 0 Data Receive Register 1
McBSP 0 Data Transmit Register 2
McBSP 0 Data Transmit Register 1
Timer Register
Timer Period Register
Timer Control Register
Reserved
Software Wait-State Register
Bank-Switching Control Register
Reserved
Software Wait-State Control Register
HPI Control Register (HMODE = 0 only)
Reserved
McBSP 2 Data Receive Register 2
McBSP 2 Data Receive Register 1
McBSP 2 Data Transmit Register 2
McBSP 2 Data Transmit Register 1
McBSP 2 Subbank Address Register
(1)
McBSP 2 Subbank Data Register
(1)
Reserved
McBSP 0 Subbank Address Register
(1)
McBSP 0 Subbank Data Register
(1)
Reserved
General-Purpose I/O Control Register
General-Purpose I/O Status Register
Device ID Register
Reserved
McBSP 1 Data Receive Register 2
McBSP 1 Data Receive Register 1
McBSP 1 Data Transmit Register 2
McBSP 1 Data Transmit Register 1
Reserved
McBSP 1 Subbank Address Register
(1)
McBSP 1 Subbank Data Register
(1)
Reserved
DMA Priority and Enable Control Register
DMA Subbank Address Register
(2)
DMA Subbank Data Register with Autoincrement
(2)
DMA Subbank Data Register
(2)
Clock Mode Register (CLKMD)
Reserved
(1)
(2)
See Table 3-19 for a detailed description of the McBSP control registers and their subaddresses.
See Table 3-20 for a detailed description of the DMA subbank addressed registers.
48
Functional Overview
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