
Electrical Specifications
99
March 2004 Revised October 2004
SGUS051A
Table 65. XCLKIN Timing Requirements PLL Bypassed or Enabled
NO.
MIN
MAX
UNIT
C8
tc(CI)
Cycle time, XCLKIN
6.67
250
ns
C9
tf(CI)
Fall time, XCLKIN
Up to 30 MHz
6
ns
30 MHz to 150 MHz
2
C10
tr(CI)
Rise time, XCLKIN
Up to 30 MHz
6
ns
30 MHz to 150 MHz
2
C11
tw(CIL)
tw(CIH)
Pulse duration, X1/XCLKIN low as a percentage of tc(CI)
Pulse duration, X1/XCLKIN high as a percentage of tc(CI)
40
60
%
C12
40
60
%
Table 66. XCLKIN Timing Requirements PLL Disabled
NO.
MIN
MAX
UNIT
C8
tc(CI)
Cycle time, XCLKIN
6.67
250
ns
C9
tf(CI)
Fall time, XCLKIN
Up to 30 MHz
6
ns
30 MHz to 150 MHz
2
C10
tr(CI)
Rise time, XCLKIN
Up to 30 MHz
6
ns
30 MHz to 150 MHz
2
C11
tw(CIL)
Pulse duration, X1/XCLKIN low as a percentage of tc(CI)
XCLKIN
≤
120 MHz
120
<
XCLKIN
≤
150 MHz
40
60
%
45
55
C12
tw(CIH)
Pulse duration, X1/XCLKIN high as a percentage of tc(CI)
XCLKIN
≤
120 MHz
120
<
XCLKIN
≤
150 MHz
40
60
%
45
55
Table 67. Possible PLL Configuration Modes
PLL MODE
REMARKS
SYSCLKOUT
PLL Disabled
Invoked by tying XPLLDIS pin low upon reset. PLL block is completely
disabled. Clock input to the CPU (CLKIN) is directly derived from the clock
signal present at the X1/XCLKIN pin.
XCLKIN
PLL Bypassed
Default PLL configuration upon power-up, if PLL is not disabled. The PLL
itself is bypassed. However, the /2 module in the PLL block divides the clock
input at the X1/XCLKIN pin by two before feeding it to the CPU.
XCLKIN/2
PLL Enabled
Achieved by writing a non-zero value “n” into PLLCR register. The /2 module
in the PLL block now divides the output of the PLL by two before feeding it to
the CPU.
(XCLKIN * n) / 2