參數(shù)資料
型號: TMS0320F2810PBKAEP
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號處理
英文描述: Digital Signal Processors
中文描述: 數(shù)字信號處理器
文件頁數(shù): 149/159頁
文件大小: 2084K
代理商: TMS0320F2810PBKAEP
Electrical Specifications
147
March 2004 Revised October 2004
SGUS051A
Table 648. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)
NO.
MASTER
SLAVE
UNIT
MIN
MAX
MIN
MAX
M39
tsu(DRV-CKXH)
th(CKXH-DRV)
tsu(FXL-CKXH)
tc(CKX)
Setup time, DR valid before CLKX high
P10
8P10
ns
M40
Hold time, DR valid after CLKX high
P10
8P10
ns
M41
Setup time, FSX low before CLKX high
16P+10
ns
M42
Cycle time, CLKX
2P
16P
ns
Table 649. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)
NO.
PARAMETER
MASTER
SLAVE
UNIT
MIN
MAX
MIN
MAX
M34
th(CKXL-FXL)
td(FXL-CKXH)
Hold time, FSX low after CLKX low
P
ns
M35
Delay time, FSX low to CLKX high
2P
ns
M37
tdis(CKXL-DXHZ)
Disable time, DX high impedance following last data bit
from CLKX low
P + 6
7P+6
ns
M38
td(FXL-DXV)
Delay time, FSX low to DX valid
6
4P + 6
ns
2P = 1/CLKG
For all SPI slave modes, CLKX has to be minimum 8 CLKG cycles. Also CLKG should be LSPCLK/2 by setting CLKSM = CLKGDV = 1. With
maximum LSPCLK speed of 75 MHz, CLKX maximum frequency will be LSPCLK/16 , that is 4.5 MHz and P =13.3 ns.
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
CLKX
FSX
DX
DR
M35
M37
M40
M39
M38
M34
LSB
MSB
M41
M42
Figure 644. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
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