參數(shù)資料
型號(hào): TMS0320F2810PBKAEP
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號(hào)處理
英文描述: Digital Signal Processors
中文描述: 數(shù)字信號(hào)處理器
文件頁數(shù): 134/159頁
文件大?。?/td> 2084K
代理商: TMS0320F2810PBKAEP
Electrical Specifications
133
March 2004 Revised October 2004
SGUS051A
6.29
XHOLD/XHOLDA Timing
Table 637. XHOLD/XHOLDA Timing Requirements (XCLKOUT = XTIMCLK)
MIN
MAX
UNIT
td(HL-HiZ)
td(HL-HAL)
td(HH-HAH)
td(HH-BV)
When a low signal is detected on XHOLD, all pending XINTF accesses will be completed before the bus is placed in a high-impedance state.
The state of XHOLD is latched on the rising edge of XTIMCLK.
Delay time, XHOLD low to Hi-Z on all Address, Data, and Control
4tc(XTIM)
5tc(XTIM)
3tc(XTIM)
4tc(XTIM)
ns
Delay time, XHOLD low to XHOLDA low
ns
Delay time, XHOLD high to XHOLDA high
ns
Delay time, XHOLD high to Bus valid
ns
á
á
áá
áá
XCLKOUT
(/1 Mode)
XHOLD
XR/W,
XZCS0AND1,
XZCS2,
XZCS6AND7
XD[15:0]
Valid
XHOLDA
td(HL-Hiz)
td(HH-HAH)
High-Impedance
XA[18:0]
Valid
Valid
High-Impedance
td(HH-BV)
td(HL-HAL)
See Note A
See Note B
NOTES: A. All pending XINTF accesses are completed.
B. Normal XINTF operation resumes.
Figure 635. External Interface Hold Waveform
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